Home
TECHNICAL PAPERS

Costs of Static HW Partitioning on RISC-V

popularity

A new technical paper titled “Static Hardware Partitioning on RISC-V — Shortcomings, Limitations, and Prospects” was published by researchers at Technical University of Applied Sciences (Regensburg, Germany) and Siemens AG (Corporate Research).

Abstract
“On embedded processors that are increasingly equipped with multiple CPU cores, static hardware partitioning is an established means of consolidating and isolating workloads onto single chips. This architectural pattern is suitable for mixed-criticality workloads that need to satisfy both, real-time and safety requirements, given suitable hardware properties.

In this work, we focus on exploiting contemporary virtualisation mechanisms to achieve freedom from interference respectively isolation between workloads. Possibilities to achieve temporal and spatial isolation-while maintaining real-time capabilities-include statically partitioning resources, avoiding the sharing of devices, and ascertaining zero interventions of superordinate control structures. This eliminates overhead due to hardware partitioning, but implies certain hardware capabilities that are not yet fully implemented in contemporary standard systems. To address such hardware limitations, the customisable and configurable RISC-V instruction set architecture offers the possibility of swift, unrestricted modifications.

We present findings on the current RISC-V specification and its implementations that necessitate interventions of superordinate control structures. We identify numerous issues adverse to implementing our goal of achieving zero interventions respectively zero overhead: On the design level, and especially with regards to handling interrupts. Based on micro-benchmark measurements, we discuss the implications of our findings, and argue how they can provide a basis for future extensions and improvements of the RISC-V architecture.”

Find the technical paper here. Published August 2022.

Authors: Ralf Ramsauer, Stefan Huber, Konrad Schwarz, Jan Kiszka, Wolfgang Mauerer. arXiv:2208.02703v1

Related Reading
Why RISC-V Is Succeeding
Interest in this particular ISA is expanding, but the growth of other open-source hardware is less certain.
RISC-V Knowledge Center
How To Optimize A Processor
There are at least three architectural layers to processor design, each of which plays a significant role.
New Uses For AI In Chips
ML/DL is increasing design complexity at the edge, but it’s also adding new options for improving power and performance.



Leave a Reply


(Note: This name will be displayed publicly)