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New Transistor Structures At 3nm/2nm

Gate-all-around FETs will replace finFETs, but the transition will be costly and difficult.

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Several foundries continue to develop new processes based on next-generation gate-all-around transistors, including more advanced high-mobility versions, but bringing these technologies into production is going to be difficult and expensive.

Intel, Samsung, TSMC and others are laying the groundwork for the transition from today’s finFET transistors to new gate-all-around field-effect transistors (GAA FETs) at the 3nm and 2nm nodes, starting either next year or in 2023. GAA FETs hold the promise of better performance, lower power, and lower leakage, and they will be required below 3nm, when finFETs run out of steam. But even though these newfangled transistors are considered an evolutionary step from finFETs, and they have been in R&D for years, any new transistor type or material is a huge undertaking for the chip industry. Chipmakers have been postponing the move as long as possible, but to continue shrinking, GAA FETs are required.

There are several types of GAA architectures in R&D, although vendors are focusing on one version, dubbed nanosheet FETs. Basically, a nanosheet FET is a finFET on its side with a gate wrapped around it, enabling higher performance chips at lower power.


Fig. 1: Planar transistors vs. finFETs vs. gate-all-around Source: Lam Research

“GAA technology is critical for the continued scaling of the transistor. A key characteristic of 3nm GAA is threshold voltage, which can be 0.3V. This enables significantly better switching with lower standby power compared to 3nm finFETs,” said Handel Jones, CEO of IBS. “Product design costs for 3nm GAA should not be significantly different from 3nm finFETs. But the key challenge is IP qualification for GAA, which will cost 1.5 times what it costs for a 3nm finFET.”

Moving to any new transistor technology is challenging, and the rollout schedule for nanosheet FETs varies by foundry. For example, Samsung is shipping various processes based on finFETs at 7nm and 5nm, with plans to introduce nanosheets at 3nm in 2022/2023. Meanwhile, TSMC will extend the finFET to 3nm, but will migrate to nanosheet FETs at 2nm in 2024/2025, according to IBS. Intel and others also are working on nanosheets.

Nanosheet FETs incorporate several components, including a channel, which allows electrons to flow through the transistor. The first nanosheet FETs will consist of traditional silicon-based channel materials, but the next-generation versions likely will incorporate so-called high-mobility channel materials. These materials enable electrons to move faster in the channel, boosting the performance of the device.

High-mobility channels are not new and have been used in transistors for years. But these materials present some integration challenges for nanosheets, and vendors are taking different approaches to develop them:

  • At IEDM, Intel presented a paper on a nanosheet pMOS device with strained silicon-germanium (SiGe) channel materials. Intel developed the device using what some call a channel-first process.
  • IBM is developing a similar SiGe nanosheet using a different channel-last process.
  • Other channel materials are in R&D.

Chip scaling challenges
The number of companies that can afford to manufacture advanced-node chips has been shrinking with the process geometry, which is becoming more expensive with each new node. TSMC’s most advanced 300mm fab cost $20 billion.

For decades, the IC industry kept pace with Moore’s Law, doubling transistor density every 18 to 24 months in order to add more functions onto a die. But as the cost of each new process node rises, the cadence has slowed. That was first observed at 20nm, when planar transistors ran out of steam and needed to be replaced by finFETs, and it may slow further with the introduction of GAA FETs.

FinFETs helped significantly with current leakage at 22nm and 16/14. “As compared to prior planar transistors, the fin, contacted on three sides by the gate, provides much better control of the channel formed within the fin,” said Nerissa Draeger, director of university engagements at Lam Research.

At 7nm and below, static leakage has become increasingly problematic again, and the power and performance benefits have started to diminish. In the past, chipmakers could expect transistor specs to scale by 0.7X, with a 40% boost in performance for the same amount of power and a 50% reduction in area. Performance increases are now somewhere in the 15% to 20% range, and they require more complex processes, new materials and different manufacturing equipment to obtain those results.

To keep costs down, chipmakers have started to deploy new architectures that are more heterogeneous than in the past, and they have become more choosy about what gets manufactured at the latest process node. Not all chips require finFETs. Analog, RF and others are built around more mature processes and are still in high demand.

But digital logic continues to scale, and new transistor structures are in R&D at 3nm and beyond. The big question is how many companies will continue to fund this continued shrinking of features, and how effectively these advanced-node chips can be integrated with more mature processes in the same package or system.

“It is really about die economics,” said Walter Ng, vice president of business development at UMC. “At bleeding-edge nodes, wafer costs are astronomical, so few customers and few applications can afford to take advantage of expensive process technology. Even for customers that can afford the cost, some of their die sizes are running up against the maximum reticle size. That, of course, results in yield challenges.”

There is still enormous demand for chips at trailing- and leading-edge nodes. “There is a bifurcation in the chip industry where supercomputing needs, including deep learning and other applications, are driving an insatiable demand for more and more computing power that will come from 3nm, 2nm and beyond,” said Aki Fujimura, CEO of D2S. “Meanwhile, IoT and other high-volume, low-cost applications will continue to use the trailing edge.”

Why nanosheets?
At the leading edge, though, there are several hurdles that need to be overcome. FinFETs approach their practical limit when the fin width reaches 5nm, which equates to the 3nm node. The contacted poly pitch (CPP) for finFETs reaches the limit around 45nm with a metal pitch at 22nm. The CPP measures from one transistor’s gate contact to the gate contact on the adjacent device.

Once finFETs run out of steam, chipmakers will migrate to nanosheet FETs at 3nm/2nm and perhaps beyond. FinFETs are still viable for chips from 16nm/14nm to 3nm, while planar transistors will remain the mainstream technology at 22nm and above.

Gate-all-around is different than finFETs. “Gate-all-around, or GAA transistors, are a modified transistor structure where the gate contacts the channel from all sides and enables continued scaling,” Lam’s Draeger explained. “Early GAA devices will use vertically-stacked nanosheets. They are constructed of separate horizontal sheets, surrounded by gate materials on all sides. This provides improved channel control relative to finFETs.”

In nanosheet FETs, each tiny sheet makes up a channel. The first nanosheet FETs will incorporate silicon-based channel materials for both pFET and nFET devices. Second-generation nanosheets likely will use high-mobility materials for pFET, while nFET will continue to use silicon.

A nanosheet FET consists of two or more sheets. Recently, Leti demonstrated a nanosheet FET with seven sheets. A seven-sheet GAA has a “3X improvement over the usual 2-level stacked nanosheet GAA transistors,” said Sylvain Barraud, a senior integration engineer at Leti, in a paper.

On the surface, the scaling benefits between 3nm finFETs and nanosheets appear to be minimal. Initially, a nanosheet FET could have a 44nm CPP with a 12nm gate length.

But nanosheets have several advantages over finFETs. With finFETs, the width of the device is quantized. In nanosheets, though, IC vendors have the ability to vary the widths of the sheets in the transistor. For example, a nanosheet with a wider sheet provides more drive current and performance. A narrow nanosheet has less drive current, but takes up a smaller area.

“GAA architectures improve the short-channel control for further gate length scaling and stacked nanosheets improve drive strength per footprint,” said Sri Samavedam, senior vice president of CMOS technologies at Imec, in a paper.

Besides the technical merits, nanosheet FETs are being developed at select foundries, giving customers various options, as well as some difficult choices.

As it stands today, Samsung plans to introduce the world’s first nanosheets at 3nm in 2022/2023. “Initial production has a 50% probability of being in Q4/2022. High-volume production with D of <0.08 has a 60% probability in Q2 to Q3/2023,” IBS’ Jones said.

But moving to a new transistor involves some cost and time-to-market risks. With that in mind, customers have other options. For example, TSMC plans to extend finFETs to 3nm and then will move to nanosheets.

“Samsung is the clear leader in 3nm GAA, but TSMC is also developing 2nm GAA for 2024 to 2025,” Jones said. “TSMC has demonstrated excellent marketing skills to get a number of large customers to implement designs in their 3nm finFET technology.”

Regardless, the cost to develop chips at 5nm/3nm and beyond is astronomical. So customers are looking for alternatives, such as advanced packaging.

“As chip scaling has made it more and more difficult to come up with smaller transistors at new nodes, the emphasis has shifted to other areas where you can get the benefits of lower power consumption, speed and higher memory in the packaging area,” said Subodh Kulkarni, president and CEO of CyberOptics.

Making nanosheets
At some point, leading-edge IC vendors will migrate to GAA architectures like nanosheets, which are new and involve various manufacturing challenges.

“Like the transition from planar to finFET, the transition from finFET to GAA will be tough, but only in a few very specific ways,” said David Fried, vice president of computational products at Lam Research. “When moving to finFETs, the big challenge was optimizing a device on a vertical sidewall, so a lot of surface preparation and deposition challenges came up. Now, with GAA, we have to optimize a device on the underside of the structure. These same surface preparation and deposition challenges become even more challenging here.”

Etch, a process that removes materials in structures, is also challenging here. “With planar devices, it was usually pretty clear when you needed a process that is isotropic (conformal) versus a process that is anisotropic (directional),” Fried said. “With finFET, this got a little trickier. With GAA, this problem gets really rough. Some processes need to be isotropic in some places like etching under the nano-wire/sheet and also anisotropic. This becomes a process challenge and an integration challenge.”


Fig. 2: Process flow for stacked nanosheet FETs. Source: Leti/Semiconductor Engineering

In a process flow, a nanosheet FET starts with the formation of a super-lattice structure on a substrate. An epitaxial tool deposits alternating layers of SiGe and silicon on the substrate. At a minimum, a stack would consist of three layers of SiGe and three layers of silicon.

The next step is to develop tiny vertical fins in the super-lattice structure. Each fin is separate with a space in-between them. In the fab flow, the fins are patterned using extreme ultraviolet (EUV) lithography, followed by an etch process.

“A GAA transistor is only as good as its weakest channel, thereby requiring individual nanosheet dimensional control metrology,” said Scott Hoover, senior director of strategic product marketing at Onto Innovation. “Fin formation through a super-lattice requires individual layer control for thickness, composition, and silicon sheet CDs.”

Then comes one of the harder steps — the formation of the inner spacers. First, the outer portions of SiGe layers in the super-lattice structure are recessed using a lateral etch process. This creates small spaces, which are filled with dielectric materials.

“Controlling process variation for the inner spacer recess etch is very difficult because there is no etch stop,” said Robert Clark, senior member of the technical staff at TEL. “Ideally, you are trying to recess the sacrificial epi between the nanowires only where it passes through the sidewall spacers, and then replace that epi layer with a dielectric inner spacer. It’s a critical ~5nm recess etch with no line of sight and no etch stop. That’s the process equivalent of a tightrope walk with no net.”

There are other challenges. “The inner spacer module is critical for the definition of key final transistor features and control of this module is critical to minimize transistor variability. The inner spacer module provides control of the effective gate length and also isolates the gate from the source/drain epi,” said Andrew Cross, process control solutions director at KLA. “During this module, the SiGe is indented, then inner spacers are deposited and recessed. At each of these steps in the inner spacer formation, precise control of the shape and CD of the indents and final spacer recess is critical to ensure correct device performance. Moreover, control is required for each individual channel in the stack.”

Then, the source/drain are formed, followed by the channel release process. For this, the SiGe layers in the super-lattice structure are removed using an etch process. What’s left are silicon-based layers or sheets, which make up the channels.

“This step is where the GAA structures are separated from each other, which can lead to challenging buried defect types, such as residues between nanosheets, damage to the nanosheets, or selective damage to source/drain regions adjacent to the nanosheets themselves,” Cross said.

There are even more challenges. “Channel release requires individual control of sheet height, corner erosion, and channel bending,” Onto’s Hoover said.

High-k/metal-gate materials are deposited in the structure. And finally, the copper interconnects are formed, resulting in a nanosheet FET. “The other modules that may change are the bottom isolation of the device and the workfunction metal/layers to accommodate the nanosheets, but those rely mainly on processes that were already known/developed in the industry and aren’t considered to be as difficult as the inner spacer formation. Of course, even the modules that aren’t new or changing radically continue to get more and more difficult as devices scale,” TEL’s Clark said.

High-mobility devices
The first nanosheet FETs will incorporate silicon-based channels. In theory, these nanosheets are supposedly superior to finFETs, but that’s not always the case.

“Going from finFET to nanosheets, we’ve observed a large improvement of the mobility of the electrons (for nFET). The problem would be a degradation of the pFET hole mobility. That’s what we need to address,” said Nicolas Loubet, manager of equipment & unit process R&D at IBM, in a presentation.

In other words, chipmakers need to improve the pFET performance in nanosheets. So vendors are developing second-generation nanosheet FETs with improved pFETs. Second-generation nanosheets will continue to use silicon-based channels for nFET as they provide more than enough performance.

To boost the pFET, chipmakers are working on high mobility channel materials. The leading material contender is SiGe, although III-V materials, germanium and other technologies are in R&D.

“Strained SiGe recently emerged as a promising pFET channel alternative to silicon due to both its superior hole mobility and mature processing in view of mass production,” said Ashish Agrawal, a device engineer at Intel, in a paper.

To integrate these materials in devices, chipmakers implement so-called strain engineering processes in a fab. Strain is a type of stress that is applied to silicon to improve electron mobility.

Strain engineering isn’t new. For years, chipmakers have used SiGe alloy stressors in the channel to boost carrier mobility. “Strain engineering has been one of the key techniques in CMOS technologies,” said Shogo Mochizuki, a senior researcher at IBM. “From the 90nm node, source-drain epi growth induced strain in the channel to help the mobility. It is still being used in finFETs.”

So it’s only natural that chipmakers will introduce strain SiGe channel materials in next-generation GAA transistors, but that adds some new challenges. “We propose replacing channel silicon with channel SiGe. This can help to boost strain and mobility. In addition, this innovation helps an ultra low-Vt device obtain superior reliability, which cannot be offered by source-drain epitaxy base strain engineering,” Mochizuki said. “The largest challenges for nanosheets with new channel materials are ensuring uniformity and structural integrity of the materials, as well as ensuring that the new channel materials are compatible with the downstream process.”

On top of that, there are several ways to develop SiGe pFET channels, including a channel first versus a channel last process.

At IEDM, Intel presented a paper on a SiGe nanosheet pMOS device on a strain relaxed buffer (SRB). The nanosheet channel is based on compressively strained SiGe with a mix of Si0.4Ge0.6. The pMOS device consists of a 5nm sheet thickness with a 25nm gate length.

For this, the channel formation takes place in the early or first stages in a conventional nanosheet process. In many respects, this a SiGe channel first process.

Intel’s process starts with a 300mm substrate. A SiGe-based SRB layer is grown on the substrate. Then, alternating layers of compressive Si0.4Ge0.6 and tensile silicon are grown on the SRB layer.

This creates a super-lattice structure, which forms the basis of a SiGe channel for pFET. “In this work, we demonstrate a buried Si0.7Ge0.3 SRB global stressor to induce compressive strain in Si0.4Ge0.6 pFET nanosheets, resulting in enhanced hole transport,” Intel’s Agrawal said.

Another term for SRB is a virtual substrate. “Traditionally, the silicon substrate determines the lattice constant of all the epitaxial layers deposited or grown on top of it. The nature of strain in the channel and source/drain are determined by the relative difference of the lattice constant between that layer with respect to the silicon substrate,” Agrawal said. “For the case of SRB or virtual substrate, we changed the lattice constant of the substrate itself by growing a relaxed Si0.7Ge0.3 buffer on top of silicon substrate. All the subsequent layers deposited on top of this buffer will be strained with respect to the Si0.7Ge0.3. By changing the lattice constant of the substrate in the form of a relaxed Si0.7Ge0.3 buffer, we can achieve strained nanosheet CMOS.”

Others are taking different approaches. For example, at IEDM, IBM presented a paper on a nanosheet pFET with a strained SiGe channel using a channel last process.

Using this approach, IBM’s pFET nanosheet demonstrated a 100% uplift in peak hole mobility with a corresponding channel resistance reduction of 40%, while maintaining a sub-threshold slope below 70mV/dec.


Fig. 3: Cross-sectional STEM image and EDX element map of stacked SiGe NSs channel with 4 nm-thick Si0.65Ge0.35 epitaxial growth along the gate post M1. Wsheet = 40 nm. Source: IBM

IBM developed a SiGe channel in the latter part of the process, not in the beginning. “We realized that starting with SiGe growth epitaxy early in the process is not effective for strain. It also brings complexity and cost in the integration process,” IBM’s Mochizuki said. “With our novel technique, the strain in the SiGe layer is preserved. This occurs because this process is based on an SiGe epitaxy-last scheme, which is essential for performance enhancement.”

More specifically, IBM develops the SiGe channels later and after the channel release process. “After the channel release, the silicon nanosheet is trimmed both horizontally and vertically. Then, we wrap a SiGe selective wrapping, known as SiGe cladding, around the trimmed silicon nanosheet,” Mochizuki said. “The final structure has SiGe cladding with a thin silicon nanosheet core. By confining carriers within the SiGe cladding layer, we can obtain an improvement in carrier mobility in the strained SiGe channel layer.”

Conclusion
Gate-all-around has several manufacturing challenges, and the cost is so high that it’s not clear how many chipmakers will be able to afford it. Fortunately, though, it’s not the only option on the table. Advanced packaging and new device architectures will almost certainly play a bigger role for current and future devices.

Still, no one technology can meet all needs. So at least for now, the industry likely will embrace all of them.

Related
GAA FET Knowledge Center
The Chip Industry’s Next-Gen Roadmap
SRC’s new CEO sheds some light on next-gen projects involving everything from chiplets to hyperdimensional computing and mixed reality.
Making Chips At 3nm And Beyond
Lots of new technologies, problems and uncertainty as device scaling continues.
Variation Threat In Advanced Nodes, Packages Grows
Complex interactions and tighter tolerances can impact performance, power and life expectancy.
Challenges In Stacking, Shrinking And Inspecting Next-Gen Chips
One-on-one with Lam CTO Rick Gottscho.



10 comments

Tanj Bennett says:

the IBM cross sections appear to have poor Ti gate fill between the sheets. Was there any discussion of that?

The next puzzle seems to be how to put both P and N FETs into the same process, especially if stacked vertical pairs around the 2N node. The layers are all propared on a blank wafer, right? Then the etching begins. Differentiating side by side seems just a matter of masking, but how will they differentiate vertically? Fun. Do they planarize the lower set then add a new set of layers and work another set of devices above some barrier layer? Carrying the crystal structure would then be interesting.

Victor Avendano says:

Interesting reading. Describe what chipmakers are doing for the next transistor generation. Still it is the concern if makes sense to move to those tech nodes because the cost not only manufacturing also design, verification, engineering hours of extra effort to achieve time to market, etc.
Thanks for sharing.

Karey Holland, PhD says:

At what “node” of GAA do you expect the buried power rails to arrive. I’m hearing not on the first GAA product nodes. And, when do you think we’ll see the imec ForkSheets or stacked nanosheets (CFETs)>

Mark LaPedus says:

Hi Tanj and Karey,

Tanj, I believe you are referring to CFETs. ”CFET devices, where the N and P devices are stacked on top of each other, are very promising for logic and SRAM scaling,” according to Imec.

CFETs are difficult. Coventor has some blogs on this subject:
https://www.coventor.com/blog/introducing-nanosheets-complementary-field-effect-transistors-c-fet/

Karey,
First, the industy will introduce nanosheets FETs at 3nm/2nm. Beyond that, the roadmap is cloudy. Buried power rails may appear with nanosheets, but that’s unclear.

Then, the roadmap is very, very, very cloudy. According to Imec’s roadmap, forksheets are slated for the latter part of 2nm. CFETs are targeted for the 1.5nm node, according to Imec. The dates are unclear. And this may or may not happen. Hard to predict.

There are so many challenges. See:
Making Chips At 3nm And Beyond

https://semiengineering.com/making-chips-at-3nm-and-beyond/

Ben says:

How much more atomic layer deposition will this require?

Mark LaPedus says:

Hi Ben. That’s very difficult to quantify. It depends on process, volumes, etc. Too early to say.

Dryiceboy says:

Intersting article!
But my question is:
Intel are using substrate induced strain, but nanosheet device has multi-sheet, it’s easy for the lowest sheet to use this substrate induced strain but what about the other sheets above?

dryiceboy says:

also, does it means the gate could lose control for at least one-side of the channel due to this substrate induced strain?

Tanj says:

Forksheets look like fins turned sideways, only surrounded on 3 sides just like fins. So, will they revert to longer channels but still be worth using, due to layout efficiency?

Or is there some reason they actually can have shorter channels than finFETs?

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