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International Roadmap for Devices and Systems lithography roadmap


Abstract: "Background: Planned improvements in semiconductor chip performance have historically driven improvements in lithography and this is expected to continue in the future. The International Roadmap for Devices and Systems roadmap helps the industry plan for the future. Aim: The 2021 lithography roadmap shows requirements, possible options, and challenges for the next 15 years. Resul... » read more

High-NA EUVL: the next major step in lithography


"In the course of 2025, we expect to see the introduction of the first high-NA extreme ultraviolet (EUV) lithography equipment in high-volume manufacturing environments. These next-generation lithography systems will be key to advance Moore’s Law towards the logic 2nm technology generation and beyond. In this article, imec scientists and engineers involved in preparing this major engine... » read more

Will AI Drive Scaling Forward?


The almost ubiquitous rollout of AI and its offshoots—machine learning, deep learning, neural nets of all types—will require significantly more processing power as the amount of data that needs to be processed continues to grow by orders of magnitude. What isn't clear yet is how that will affect semiconductor manufacturing or how quickly that might happen. AI is more than the latest buz... » read more

EUV’s Uncertain Future


The ground appears to be solidifying under EUV. Intel announced this week it is reducing its stake in ASML to less than 3%, the second such move in a year. Apparently ASML no longer needs outside help. According to the company's earnings report, ASML turned in net sales of €2.776 billion, a slight increase over the €2.447 billion (GAAP) the company reported in Q3 and way up over the €... » read more

More Lithography/Mask Challenges (Part 3)


Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; Regina Freed, managing director of patterning technology at [getentity id="... » read more

Next EUV Issue: Mask 3D Effects


As extreme ultraviolet (EUV) lithography moves closer to production, the industry is paying more attention to a problematic phenomenon called mask 3D effects. Mask 3D effects involve the photomask for EUV. In simple terms, a chipmaker designs an IC, which is translated from a file format into a photomask. The mask is a master template for a given IC design. It is placed in a lithography scan... » read more

More Lithography/Mask Challenges (Part 2)


Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; Regina Freed, managing director of patterning technology at [getentity id="... » read more

DSA Re-Enters Litho Picture


By Mark LaPedus and Ed Sperling Directed self-assembly (DSA) is moving back onto the patterning radar screen amid ongoing challenges in lithography. Intel continues to have a keen interest in [gettech id="31046" t_name="DSA"], while other chipmakers are taking another hard look at the technology, according to multiple industry sources. DSA isn't like a traditional [getkc id="80" kc_name="... » read more

Exponentials At The Edge


The age of portable communication has set off a scramble for devices that can achieve almost anything a desktop computer could handle even five years ago. But this is just the beginning. The big breakthrough with mobile devices was the ability to combine voice calls, text and eventually e-mail, providing the rudiments of a mobile office-all on a single charge of a battery that was light enou... » read more

Is Advanced Packaging The Next SoC?


Device scaling appears to be possible down to 1.2nm, and maybe even beyond that. What isn't obvious is when scaling will reach that node, how many companies will actually use it, or even what chips will look like when foundries actually start turning out these devices using multi-patterning with high-NA EUV and dielectrics with single-digit numbers of atoms. There are two big changes playing... » read more

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