EUV’s Uncertain Future At 3nm And Below

Manufacturing chips at future nodes is possible from a technology standpoint, but that’s not the only consideration.


Several foundries have moved extreme ultraviolet (EUV) lithography into production at both 7nm and 5nm, but now the industry is preparing for the next phase of the technology at 3nm and beyond.

In R&D, the industry is developing new EUV scanners, masks and resists for the next nodes. 3nm is slated for 2022, followed by 2nm a year or two later. Nonetheless, it will require massive funding and time to develop future EUV technologies, and the return on investment is unclear.

Used in advanced fabs, EUV involves a giant and expensive lithography scanner, which patterns tiny features on chips at 13.5nm wavelengths. EUV is one of several fab tools used in chip scaling. This is where you shrink different chip functions at each node and pack them onto a monolithic die. But chip scaling is becoming more expensive at each generation, and the benefits are diminishing.

“You need to think about cost holistically,” said David Fried, vice president of computational products at Lam Research and CTO at Coventor. “It’s performance per power unit or price. If cost isn’t the motivator for the next node, then it has to be something else that is very compelling, such as increased function density within a certain area. You need to achieve either a massive performance benefit or a straight up cost per unit/function benefit. Otherwise, you’re not going to undertake the time, development cost and risk to build the chip.”

Chip scaling helps provide a performance boost for certain devices, such as DRAMs, FPGAs, GPUs and processors, at each generation. AI, automotive, servers and wireless need faster chips with more functions. Of course, not all chips require advanced nodes.

EUV, along with other equipment and materials, will help pave the way for current and future devices. But all of this requires R&D and funding. For example, the industry has poured billions of dollars in funding for EUV since the technology was conceived in the 1980s and 1990s. And after years of delays, chipmakers only recently have put EUV into production.

Going forward, EUV will require more R&D and funding. But at some point, the industry will need to recoup its investments, which could take years.

“For a single company that fabricates chips, it has been estimated that a minimum initial capital investment of one billion dollars is needed to start using EUV lithography in high-volume manufacturing,” said Harry Levinson, principal at HJL Lithography, in a recent paper. “Companies producing the key elements of EUV infrastructure, such as mask blanks, inspection tools, resists, and exposure systems, have also made significant investments into EUV technology. Whether or not companies realize a positive return on their investments in EUV technology is dependent on the semiconductor industry’s ability to extend the technology to future nodes and how much more investment will be required. No insurmountable problems for extensibility have been identified, but several issues need to be confronted, with solutions identified and implemented in order to extend EUV lithography beyond one or two nodes.”

Nonetheless, to extend EUV, the industry is working on several technologies. Among them:

  • In 2021, ASML will introduce an upgraded version of its current EUV scanner. A next-generation EUV system is in R&D.
  • Advanced EUV binary and phase-shift photomasks are in the works.
  • EUV pellicles and new resists are in R&D.

New scanners
In the semiconductor process flow, a chipmaker first designs an IC, which is then translated into a file format. Then, in a photomask facility, a mask is produced based on that format. The mask is a master template for an IC design.

In a fab, the mask as well as a wafer are inserted in a lithography scanner. A photoresist, a light-sensitive material, is applied on the wafer. In operation, the scanner generates light, which is transported through a set of projection optics and the mask in the system. Light then hits the resist, creating patterns on the wafer.

Defined by Rayleigh’s Equation, the resolution (R) of any lithographic system is equal to the k1 factor times the wavelength (λ) over the numerical aperture (NA). The k1 factor involves various items, such as photoresist improvements and resolution enhancement techniques (RETs). RETs are optical tricks that can boost the resolution.

For years, chipmakers used optical-based 193nm wavelength lithography scanners to pattern the most advanced features in chips. With multiple patterning, chipmakers have extended 193nm lithography down to 10/7nm. But at 5nm, the current lithographic technologies run out of steam.

That’s where EUV fits in. EUV enables chipmakers to pattern the most difficult features at 7nm and beyond. “EUV is a requirement,” said Rich Wise, managing technical director at Lam Research, in a recent interview. “We view it fundamental to the technology. It’s part of the continued scaling for the industry.”

But EUV took longer to develop amid a series of technical glitches. Finally, after years of delays, EUV recently moved into production within Samsung and TSMC at 7nm. TSMC is shipping 5nm with EUV. Intel is also developing EUV.

Chipmakers are using ASML’s EUV scanner, called the NXE:3400C. Using a 13.5nm wavelength, the 0.33 numerical aperture (NA) system has 13nm resolutions. A 246-watt source enables a throughput of 170 wafers per hour.

There are still some challenges with the uptimes for EUV, which impacts throughput. Average EUV system uptimes are reaching 85%, with the top 10% achieving 90% availability, according to ASML. In comparison, 193nm scanners operate without interruptions.

In addition, EUV is prone to unwanted variations, known as stochastic effects. In EUV, the scanner generates light or photons. In the system, light hits the resist, sending a certain number of photons into the material to create patterns.

Ideally, the photons should be evenly dispersed throughout the resist, but that doesn’t always happen. If there is a mishap in the process, EUV can cause stochastic-induced defects in chips. Those defects show up as line breaks or contact holes that merge, sometimes referred to as “missing and kissing contacts.”

In a recent paper, TEL investigated the problem involving missing hole defects in EUV patterning. TEL examined the interfacial reaction between the photoresist and underlayer. “We found out that the surface condition of the underlayer was significantly related to the stochastical scumming error in the solubilized resist region around the bottom area in the via hole. Negative tone type resist (NTD) has an advantage to reduce missing defects without resist peeling, because the developer solution for NTD has a desirable triangle balance between the resist and substrate. The important thing is to understand the resist desorption mechanism in developing the process step and to find the favorable treatment to minimize the inhibition factor of resist dissolution,” said Hidetami Yaegashi, a senior manager at TEL.

Nonetheless, EUV has taken off. “ASML continues to expect to ship 35 EUV systems in 2020, up from 26 in 2019,” said Weston Twigg, an analyst at KeyBanc. “ASML currently has around 56 EUV units on order.”

Going forward, ASML plans to ship an upgraded version of its EUV scanner by mid-2021. The system, called the NXE:3600D, is also a 0.33 NA tool with 13nm resolutions. “The 3600 has stage improvements, minor lens improvements and sensor improvements. We’ve made incremental improvements that give it a better overlay and higher productivity, but it’s functionally the same design,” said Michael Lercel, director of product marketing at ASML. “We changed the dose from 20mJ/cm2 to 30mJ/cm2 in the NXE:3600D, which better reflects the throughput improvement of customers process conditions in volume productions. So the NXE:3400C at 30mJ/cm2 would be lower than the 170wph (@20mJ) that we quoted at SPIE. The 3400C at 30mJ would be ~140wph – but that is just an estimate.”

In 2022 ASML hopes to ship a next-generation EUV system called high-NA EUV. An extension of today’s EUV, high-NA EUV is an expensive system targeted for 3nm in 2023.

The system features a 0.55 NA lens capable of 8nm resolutions. Instead of a traditional lens, the high-NA tool incorporates an anamorphic lens. This lens supports 8X magnification in the scan mode and 4X in the other direction. So the field size is reduced by half. In some cases, a chipmaker would process a chip on two masks. Then the masks are stitched together and printed on the wafer, which is a complex process.

New masks
Meanwhile, the industry also is developing new EUV mask types. Traditional optical and EUV masks are different, but the process flow is similar.

In mask-making, the first step is to create a substrate or mask blank, which consists of various materials. The materials on the blank are patterned and etched, creating a photomask.

The mask is then inspected for defects. Finally, a pellicle, a thin membrane, is mounted on top of the mask, which protects the mask from falling particles or contamination.

In optical lithography, a mask consists of an opaque layer of chrome on a glass substrate. The chrome is etched in select places, which exposes the glass substrate. The chrome materials aren’t etched in other places.

This is called a binary mask. In operation, light hits the mask and goes through the areas with the glass, which exposes the wafer. Light doesn’t go through the areas with the chrome.

Chipmakers also use a different technology called phase-shift masks in optical lithography. Developed in 1980s, phase-shift masks use different materials and structures, which improve the image quality in patterning.

There are two types of phase-shift masks, alternating and attenuated. Alternating phase-shift masks resemble a binary mask. The difference is that glass regions are made thinner or thicker.

“In an alternating aperture phase shifting mask, the light on one side of every dark line is 180 degrees out-of-phase with the light on the other side. That creates destructive interference between the apertures on either side, making the line dark even if it is out of focus a bit. This destructive interference effect also relaxes the usual wavelength-dependent Rayleigh limit on the width of a resolved feature,” explained Marc David Levenson, who invented the phase-shift mask while at IBM in the 1980s. (Levenson has since retired.)

Attenuated phase-shift masks also resemble a binary mask. The difference is that a molybdenum silicide (MoSi) material replaces the chrome. In operation, light hits the mask. “Since the MoSi is not opaque like chrome, light is partially transmitted (typically 6%) and the phase is shifted, so it is roughly 180 degrees different from the light that goes through the glass only,” explained Bryan Kasprowicz, a distinguished member of the technical staff at Photronics.

Fig. 1: A schematic illustration of various types of masks: (a) a conventional (binary) mask; (b) an alternating phase-shift mask; (c) an attenuated phase-shift mask. Source: Wikipedia

Binary, phase-shift and other mask types are proven technologies in optical lithography. In EUV, meanwhile, the industry is only using binary EUV masks. Advanced EUV-based binary masks and phase-shift masks are in R&D.

Unlike optical masks, which transmit light, today’s binary EUV masks reflect light at 13.5nm wavelengths. An EUV mask consists of 40 to 50 alternating layers of silicon and molybdenum on a substrate, resulting in a multi-layer stack that is 250nm to 350nm thick. A ruthenium capping layer is deposited on the multi-layer stack, followed by a tantalum absorber.

Fig. 2: Cross-section of an EUV mask. Source: Luong, V., Philipsen, V., Hendrickx, E., Opsomer, K., Detavernier, C., Laubis, C., Scholze, F., Heyns, M., “Ni-Al alloys as alternative EUV mask absorber,” Appl. Sci. (8), 521 (2018). (Imec, KU Leuven, Ghent University, PTB)

The absorber is a 3D-like feature that juts out on top of the mask. In operation, EUV light hits the mask at a 6° angle. The reflections potentially cause a shadowing effect or photomask-induced imaging aberrations on the wafer. This issue, known as mask 3D effects, can result in unwanted pattern placement shifts.

To mitigate these effects, one could reduce the thickness of the tantalum absorber. Tantalum absorbers are 60nm thick. But the material can only be reduced down to 55nm, which doesn’t solve the problem.

“Because of mask 3D effects, the current thickness of the tantalum needs to be reduced. When you reduce the thickness, they have issues. The absorption is not as good,” said Meng Lee, director of product marketing at Veeco.

All told, the current EUV binary masks work at 7nm/5nm, but chipmakers need a new version at 3nm and beyond. So in R&D, the industry is developing new EUV binary masks, where a high-k material like nickel or others would replace tantalum. In the lab, Imec has demonstrated a nickel-based absorber with a 30nm thickness, which reduces the 3D mask effects.

The problem is that nickel and other high-k materials are difficult to etch. “You can come up with a high-k material, but the question is, ‘Can you etch it?’ That might be a problem. Or, you can etch it, but you can’t clean it. That’s also a problem,” Lee said.

Meanwhile, in a separate effort, chipmakers are also developing EUV attenuated phase-shift masks. For this, the idea is to replace the tantalum material with a different and lower-k material. In other words, the material properties for high-k and phase-shift masks are different.

Still in R&D, EUV phase-shift masks work like both alternating and attenuated technologies. “The type of phase shifting mask that we’re considering for EUV does a little bit of both. It blocks some of the light, but not all of it. And the stuff it doesn’t block, or the light that is allowed to leak through, is out of phase with the rest of the light. You get this phase interference effect, and it gets darker. That tends to make your images a little bit better, a little steeper and a little higher contrast,” said Chris Mack, CTO of Fractilia. “Phase shifting masks have the potential of improving the contrast of the image, which could enable better printing performance. It could also enable lower stochastic variations including roughness. So there’s definitely an interest in the use of phase-shift masks.”

There are other benefits. “We’ve had phase-shifting masks for optical lithography for over 30 years,” HJL Lithography’s Levinson said. “It may be even more important for EUV because of mask 3D effects. Phase-shifting masks may have the potential to address that, but phase shifting for EUV is more complicated than optical and more development work is needed.”

Indeed, EUV phase-shift as well as advanced binary masks present some challenges. For one thing, there are several material options on the table for both with little consensus. Ruthenium is the top candidate for EUV phase-shift, though.

That’s not the only issue. “The mask industry is quite conservative and is not easily going to change materials on the blanks,” said Kurt Ronse, director of the advanced lithography program at Imec. “To change a material on the mask, there are many requirements. The materials have to withstand the scanner. There should not be any outgassing or contamination of the optics. It has to be cleanable and repairable. The materials have to be uniform, amorphous, durable against cleaning materials, and high-power EUV generating H-radicals. All these requirements have to be met by the material selected.”

Over time, though, the industry will require both advanced binary and phase-shift masks for EUV. Advanced binary masks are ideal for lines and spaces, while phase-shift is geared for contact holes and vias.

“In principle, phase-shift masks could be more effective to achieve a higher NILS than high-k binary,” said Takahiro Onoue, senior director of Hoya. “However, high-k binary masks can be applied to universal mask patterns, so they are less pattern dependent.”

Normalized image log-slope (NILS) involves the steepness of image intensity on the wafer. Nonetheless, the new EUV mask types aren’t expected to appear for two or so years.

Putting the pieces in place
To be sure, the industry is developing several new EUV technologies. So how will this all fit together?

Back in 2018, ASML’s 0.33 NA EUV scanners were inserted for production at the 7nm foundry node. 7nm has a 54nm-64nm contacted gate pitch (CPP) and a 36nm to 40nm metal pitch, according to WikiChip, a technology site.

At 7nm, chipmakers are using EUV to pattern select chip features with pitches starting at 40nm. Here, vendors are using an EUV-based single patterning approach. The idea is to put the chip features on one mask and print them on the wafer using a single lithographic exposure.

Chipmakers would like to extend EUV single patterning as far as possible, because it’s a straightforward process. There are several ways to push the technology. “You increase the throughputs, image quality, power and overlay,” said Doug Guerrero, senior technologist at Brewer Science.

Down the road, EUV phase-shift masks could help matters. Phase-shift masks won’t extend the resolutions beyond the advertised 13nm spec in EUV.

Using phase-shift, though, chipmakers could boost the contrast and push the usable resolutions a little tighter. More importantly, it addresses the 3D mask effects. “A phase-shift mask is certainly a way to get a better image. Phase-shift masks have a known benefit. It is certainly going in the right direction for extending EUV, but it’s not an overwhelming new change,” Guerrero said.

If or when it is ready, phase-shift masks provide another tool in the toolbox. “The 0.33 NA tools go down to 13nm lines and spaces. So 26nm pitch is kind of the limit for the 0.33 NA tools. Now, if you have two-dimensional features and complex features, you can’t do 26nm pitch. But with phase-shift, you get better contrast. You can push it closer,” ASML’s Lercel said. “The basic imaging resolution of the optics does not change – it is still the 26nm pitch. AttPSM masks may be able to increase the contrast slightly – allowing use at a lower k1 factor. Hence for some types of patterns, you might be able to push the usable resolution down a little closer to the limits of the optics.”

Meanwhile, TSMC is shipping its new 5nm process, which is expected to have a 48nm CPP and a 30nm metal pitch, according to WikiChip. Soon, Samsung will ship 5nm. At 5nm, TSMC is using EUV for more than 10 layers, and has reduced the mask count from about 87 at 7nm to 81 at 5nm, according to WikiChip.

At this node, chipmakers would like to use EUV single patterning for good reason. They would like to avoid EUV double patterning or minimize it as much as possible.

In double patterning, you split the features on two masks and print them on the wafer. It sounds simple, but the process is complex and expensive.

“The reason why 193nm immersion lithography is becoming more challenging is because in order to expose one layer of a wafer pattern, you have to do multiple patterning. And then you have to line them up and you have all these problems,” said Aki Fujimura, chief executive of D2S. “You want to avoid that as long as possible with EUV. So you want to stay in the single patterning area for as long as possible.”

Today, single-patterning EUV reaches the limit at 32nm-30nm pitches. If chipmakers can’t extend single patterning to a certain point, they must resort to double patterning EUV at 5nm and/or 3nm. “A way to look at this is by k1. When values of k1 went below 0.3 in optical lithography, a higher NA, double patterning or EUV was required. For insertion of EUV to HVM with a 40nm pitch, k1 is 0.49. There is room to get to 0.3 (25nm pitch), but better tools are needed, as well as a solution for mask 3D effects. Attenuated phase-shift masks can help with the mask 3D effects. We also need higher doses and better resists,” HJL Lithography’s Levinson said.

At today’s most advanced nodes, though, double patterning EUV seems unavoidable. “Manufacturers have already announced high-volume manufacturing plans for 5nm and 3nm, but today’s resists cannot meet the performance requirements for these nodes,” Lam’s Wise said. “These plans are based on the application of multiple passes of lithography per layer, where the resist requirements are relaxed by accepting increased cost and design compromises. Absent of a breakthrough in resist performance, these tradeoffs will limit the adoption of advanced nodes to the markets that can afford these high costs and design compromises.”

That’s why chipmakers are pushing for high-NA EUV at 3nm and beyond, enabling them to continue with the simpler single-patterning approach. By then, chipmakers also want the new EUV mask types to address the mask 3D effects.

The goal is to ship a high-NA EUV tool by 2022. “There is pressure to accelerate it and avoid double patterning at 0.33. If the industry can switch from single patterning 0.33 to 0.55, that will be much easier. It will take more time than we think to get high-NA EUV into manufacturing,” Imec’s Ronse said. “It’s a new body and system. Even if there is a system in 2022 or 2023, it doesn’t mean the infrastructure (resists, underlayers, masks) is ready to make sure you can implement this into high-volume manufacturing.”

There are other technologies in R&D, such as EUV pellicles, inspection tools and others. Plus, Lam Research recently announced a dry resist technology, which is in R&D and targeted for 3nm. For this, various compounds are processed in a chemical vapor deposition (CVD) system, which creates an EUV resist. Instead of spin coating, the resist is deposited on the wafers in the CVD system, which reduces resist waste in the fab.

The needs keep piling up. All of this will take time and money with an unknown return.

Related Stories

Multi-Patterning EUV Vs. High-NA EUV

Improving EUV Process Efficiency

Finding Defects In EUV Masks

5/3nm Wars Begin

Making Chips At 3nm And Beyond


F Chen says:

A number of aspects overlooked.

(1) secondary electrons form the image, not the photons directly.

(2) EUV is not just one wavelength. For 20 nm half-pitch, k1=0.5 for 13.2 nm. This is within the source bandwidth. So it’s a mixture of k1, which makes it a “dirty” imaging situation for lithography models.

(3) Besides the half-field stitching, high-NA doesn’t help because photons are divided among more pupil source points at higher k1, aggravating stochastics.


A very nice summary! Thanks!

Pankaj Doharey says:

I have a question how long can we keep going with this as I understand the a silicon atom is only 0.2 nm at 3nm EUV , the transistor width is 15 atom wide, how much smaller can we keep going till the tunnelling effects become uncontrollable?

John McKnight says:

hummm ….. ASML is in the process of buying Berliner glass. Key optical components of refined technical glass should reduce the distortion of photons clarifying edges of the masks…resulting in increased resolution of the image. At least that is my understanding so it should allow fewer defects in future high EUV masks.

Allen Rasafar says:

Thank you for sharing this Wonderful insight.

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