Multi-Patterning EUV Vs. High-NA EUV

Next-gen litho is important for scaling, but it’s also expensive and potentially risky.


Foundries are finally in production with EUV lithography at 7nm, but chip customers must now decide whether to implement their next designs using EUV-based multiple patterning at 5nm/3nm or wait for a new single-patterning EUV system at 3nm and beyond.

This scenario revolves around ASML’s current extreme ultraviolet (EUV) lithography tool (NXE:3400C) versus a completely new EUV system with a high-numerical aperture lens (EXE:5000), which is commonly called high-NA EUV. Still in R&D, ASML’s new high-NA EUV system features a radical 0.55 NA lens capable of 8nm resolutions. An extension of the current NA system, the 0.55 NA tool is targeted for the 3nm node in 2023, but it will likely appear at a later node, such as 2nm. The mammoth-size tool is extremely complex and expensive.

Nevertheless, Intel and others are pushing to accelerate the development of the high-NA EUV system. Those chipmakers would prefer to avoid multi-patterning EUV at 5nm and/or 3nm, and instead migrate to the next nodes using single patterning with high-NA. That’s not to say multi-patterning EUV will never get deployed. It might get used when needed or if there’s no other option.

Today, Samsung and TSMC are making 7nm chips using ASML’s existing EUV tool, which incorporates a 0.33 NA lens. At 7nm, chipmakers are patterning the tiny chip features using an EUV-based single patterning approach, which creates patterns with a single lithographic exposure.

At 5nm, chipmakers might use ASML’s existing 0.33 NA EUV tool, which could require single and/or double patterning EUV. At one point, double patterning EUV appeared to be straightforward. But there are growing concerns that double patterning EUV is too complicated and expensive for many devices. And at 3nm, triple patterning EUV may be necessary, which is not considered viable.

So chipmakers will extend single patterning EUV as long as possible, which is somewhere around 30nm-28nm pitches. “If you want to go below 28nm pitches, you have a choice of double patterning, triple patterning or high-NA. Everyone would like to have high-NA. The best thing to do is 28nm at the existing numerical aperture, then go to high-NA, and finally go to multiple patterning,” said Harry Levinson, principal at HJL Lithography.

So, it’s imperative to develop high-NA. “In parallel with continued improvements to 0.33, we need to develop 0.55,” said Mark Phillips, an Intel fellow and director of lithography hardware and solutions at the chip giant, in a recent presentation. “Intel has a robust roadmap of process nodes that requires the resolution and EPE (edge placement error) benefits of continued EUV lithography development. High-NA EUV is needed to avoid 0.33 NA mask splits, eliminates the cumulative EPE for mask splits, reduces process complexity and lowers cost. We need the ecosystem to be ready to support it by 2023.”

Speaking to lithographers and mask makers at the event, Philips’ presentation was a call to action to keep high-NA EUV on track and address the gaps with the technology, namely masks and resists. High-NA always has been targeted for 2023, but there is a danger that it could slip based on past events. Current EUV was several years late before moving into production.

And while 2023 seems far away, high-NA EUV is a massive undertaking with multiple challenges that will require time and money. It also requires collaboration across the equipment and materials supply chain. And even then, there is no guarantee it will work or keep chip scaling afloat.

Fig. 1: ASML’s High-NA EUV tool. Source: ASML

From optical to EUV
In chip scaling, chipmakers have scaled or reduced the transistor specs by 0.7X at each node, thereby reducing the cost per transistor. This, in turn, enables the development of new electronic products with more functions.

Making chips was a straightforward process until 20nm, when planar transistors hit the wall. Starting in 2011, chipmakers moved to finFET transistors at 22nm and 16nm/14nm.

FinFETs are faster and require less power, but they are difficult and expensive to make. So now the cadence for a scaled node has extended from 18 months to 2.5 years or longer.

Lithography, a key part of chip scaling that patterns features on chips, also hit a roadblock at 20nm. The lithography process starts with a photomask. A chipmaker designs an IC, which is translated from a file format into a photomask. The mask is a master template for an IC design.

In the fab, the mask is placed in the lithography scanner. A wafer is moved into the scanner. The scanner projects light through the mask onto the wafer, creating patterns on the wafer.

This is a straightforward process at 28nm and above. Design features are assembled on one mask and a scanner patterns them on a wafer using a single lithographic exposure, which is a single patterning process.

At 20nm, the design features became too dense on the mask, making it more difficult to print discernible features on the wafer. So chipmakers moved to multiple patterning, where the original mask shapes are relaxed and divided between two or more masks.

“Each mask is then printed separately, eventually imaging the entire set of originally-drawn shapes onto the wafer,” explained David Abercrombie, marketing director at Mentor, a Siemens Business.

To pattern these features on a wafer, chipmakers use various process schemes in the fab, such as double patterning or self-aligned schemes, which enable smaller features in chips.

Fig. 2: Self-aligned spacer avoids mask misalignment. Source: Lam Research

Fig. 3: Double patterning increases density. Source: Lam Research

Multiple patterning has extended IC scaling down to 7nm, but it also increases the complexity at each node. “The reason why 193nm immersion lithography is becoming more challenging is because in order to expose one layer of a wafer pattern, you have to do multiple patterning. And then you have to line them up and you have all these problems,” said Aki Fujimura, chief executive of D2S.

All told, chipmakers can extend 193nm/multi-patterning to 7nm, but it becomes too unwieldy and expensive at 5nm. And that’s where EUV fits in. It simplifies the process and enables chipmakers to pattern the most difficult features at 7nm and beyond. Lithography isn’t the only equipment in the fab. You also need CMP, deposition, etch, ion implantation and other systems.

Today, ASML is shipping its latest EUV scanner, dubbed the NXE:3400C. Using a 13.5nm wavelength, the 0.33 NA system enables 13nm resolutions. A 246-watt source power unit enables a throughput of 170 wafers per hour (wph).

Both Samsung and TSMC recently moved EUV into production at 7nm, with 5nm in R&D. Intel is also developing EUV.

EUV took longer than expected to develop due to various technical issues. Many are fixed, while the industry is working on the other issues, such as system uptime and EUV pellicles.

In addition, the photoresists — the light sensitive materials used to pattern images on the wafer — potentially cause random or stochastic-induced defects in chips.

At 7nm, though, the resists are less prone to stochastics. “The existing resists are adequate for the insertion point. That’s the 7nm node, roughly a 40nm minimum pitch,” HJL’s Levinson said.

The minimum pitch refers to the metal 2 (M2) structure in chips. Based on finFETs, the 7nm foundry node consists of M2 pitches between 40nm and 36nm. (Intel’s 10nm is similar to 7nm from the foundries.)

At 7nm, chipmakers are using single patterning EUV starting at 40nm pitches. Initially, EUV is likely being deployed on the difficult metal layers on chips, namely holes/vias.

Single patterning EUV works, so chipmakers will extend it as long as possible. It’s a moving target, but single patterning EUV extends down to 30nm pitches, possibly 28nm.

Now, chipmakers are readying their 5nm processes, where they will extend finFETs. TSMC’s 5nm process features a 30nm pitch.

At this pitch, chipmakers are bumping up against the limits of single pattering EUV. If chipmakers can’t extend single patterning, they will use double patterning EUV. In double patterning, you split the features on two masks and print them on the wafer using a low dose resist.

Imec and others have developed various multi-patterning EUV processes. Some experts, however, believe it’s too expensive. “I don’t think double patterning makes sense from an economic point of view,” HJL’s Levinson said. “In optical lithography, to make everything work, you have these self-aligned schemes. That’s okay in optical lithography. An optical exposure is one-third the cost of an EUV exposure. It’s a much bigger problem to add an extra EUV exposure than an extra optical one.”

In multi-patterning, the challenge is to align the different layers with each other. “Even if we apply multiple patterning techniques to EUV, overlay will be incredibly difficult,” said Doug Guerrero, senior technologist at Brewer Science.

Then, with a low dose resist, the industry assumes double patterning EUV will work. “The throughput advantage of low dose does not scale directly with the dose,” HJL’s Levinson said. “At 250-watt source power (using intermediate focus), the throughput with a resist sensitivity of 20mJ/cm2 is slightly more than 50% greater than the throughput with a resist sensitivity of 40mJ/cm2. This means that the exposure tool capital cost of double patterning at 20mJ/cm2 is about 30% greater than single patterning at 40mJ/cm2. For actual double patterning, there are the additional costs of masks, consumables and non-lithographic operations, so double exposure at low dose is a costly solution.”

What is high-NA?
Double patterning EUV is still an option at 5nm, if it’s cost-effective. But at the same time, finFETs likely will run out of steam at 5nm.

So at 3nm, chipmakers are developing a new transistor called a nanosheet FET. Slated for 2021, a nanosheet is a finFET on its side with a gate wrapped around it. The pitches range from 24nm to 21nm.

It’s unclear if the industry can stay on the roadmap. Only a handful of companies can afford those nodes. Of course, not all require advanced nodes. “The people that want extreme dimensions in logic are those in GPUs, CPUs and applications processors,” said Dan Hutcheson, chief executive of VLSI Research.

At 5nm and beyond, foundries and their customers face some intriguing decisions. At 28nm pitches and below, foundries and their customers have the following options–double patterning EUV, triple patterning EUV or high-NA, according to HJL’s Levinson.

On its roadmap, meanwhile, ASML will develop one more version of the 0.33 NA EUV system for 2021, followed by high-NA for 3nm in 2023. There is a chance ASML will meet the target. “High-NA is an extension of things we already know. In terms of getting to a higher NA, it’s mostly engineering work,” VLSI’s Hutcheson said.

Based on this timeline, high-NA won’t be ready for 3nm. If there are no major glitches, the system might be ready at the next node.

Regardless, high-NA is needed. “High-NA is likely to be used starting with the 2nm node,” said Rich Wise, managing technical director at Lam Research. “Similar to comparisons of EUV and immersion, high-NA has several value propositions. The first is the ability to reduce cycle time in the fab, as a single pass of high-NA will require less total processing than multiple passes of 0.33 NA EUV. The second is edge placement error. Dense images can be best aligned on the litho mask rather than trying to align several different steps in the fab. The third is design flexibility. Certain design elements are only possible in a single mask, and high-NA offers an improved imaging window for these elements. Yield is also closely correlated to the number of processing steps. By reducing process steps, yield is improved.”

ASML has been developing high-NA for some time. Using a 13.5nm wavelength, the 0.55 NA system has 8nm resolutions with a 180 wph throughput. “The purpose of this high-NA scanner, targeting an ultimate resolution of 8nm, is to extend Moore’s Law throughout the next decade,” said Jan van Schoot, senior principal architect at ASML.

“We see that there is a need for smaller resolutions, as well as the need to prevent double patterning. For that, high-NA is the logical successor to the 0.33 NA system for the more critical layers. 0.33 NA will then move to the layers just a little bit less critical if you look further ahead in the future,” van Schoot said. “The other reason for the high-NA tool is that we also see that we have to cope with contrast and photon shot noise. We see that we need more dose. Dose is fighting with the throughput. And for that reason, we can also help here for that with the tighter resolutions with more contrast. And if you have more contrast, then you fight this effectively, and you can keep the doses low and therefore the productivity high.”

The high-NA tool is a larger and more complex version of the current system. It incorporates faster stages. It utilizes the same laser-produced-plasma source power unit.

For high-NA, ASML will leverage many of the technologies from the current tool. Many pieces must be built from scratch. So far, ASML has finalized the system design. Zeiss is developing the high-NA optics.

Still, there are several pieces that must come together before high-NA EUV is ready, including the scanner/source unit, masks and resists.

There are major challenges in all fronts. According to HJL Lithography, the main challenges are: 1) resists; 2) source power; 3) small depths-of-focus at 0.55 NA; 4) lens polarization control; 5) stitching issues; 6) mask making; and 7) cost.

“The optical system for high-NA EUV is complex and very costly,” Brewer Science’s Guerrero said. “The optical system will be able to only do a half field, so two exposures will be required per field.”

Instead of a traditional lens design, the high-NA tool will use an anamorphic lens with a 0.55 NA. The anamorphic lens produces unequal magnifications along two axes perpendicular to each other.

Besides that, the high-NA tool operates like the current EUV system with some modifications. The process takes place in a vacuum environment, because nearly everything absorbs EUV light.

The EUV process begins within a large vessel in the scanner. In the vessel, a small droplet generator emits tiny tin droplets at a fast rate. Then, at select times, the source power unit fires two laser pulses into the vessel. The first pulse hits the droplet. The second hits the same droplet and vaporizes it. The vapor becomes plasma, which in turn emits EUV light at 13.5nm wavelengths. Then, EUV light goes through a programmable illuminator, where photons bounce off 10 multi-layer mirrors.

At that point, EUV light hits the mask. It then bounces off six multi-layer mirrors in the projection optics. Finally, the light hits the mask at a 6-degree angle. At this angle, the reflections potentially can cause a shadowing effect, resulting in photomask-induced imaging aberrations on the wafer. This is known as mask 3D effects.

The high-NA system tackles the problem, but there are some tradeoffs. In today’s 0.33 NA tool, the lens supports 4X magnification with a maximum exposure field size of 26mm x 33mm.

In high-NA, though, the anamorphic lens supports 8X magnification in the scan mode and 4X in the other direction. Increasing the image magnification from 4X to 8X boosts the resolutions and reduces the shadowing effects.

But increasing the magnification also cuts the image field size to one half. So the scanner may end up printing the features on only part of a device. This mainly involves larger die sizes.

For this, chipmakers must resort to a technique called stitching. This involves the process of exposing one part of a pattern with one mask and then exposing the next part with a second mask. Then, the masks are stitched together and printed on the wafer.

This is a complex process, which reduces the throughput to 135 wph. But to meet the 135 wph spec, ASML has devised a stocker unit for the system. The system exposes the first half-field on all wafers in a single lot. It stores the wafers in an onboard stocker. Then, it exposes the second half-field.

To get around the problem, you can develop chips with smaller die sizes. Another solution is chiplets. In chiplets, you have a library of smaller die, which are then assembled and connected in an advanced package.

Some chiplets may require advanced nodes, while others will not. Regardless, smaller dies or chiplets can be exposed within the entire half field. Therefore, they don’t require stitching. “It’s also one of the ways around the half-field-size limitation on high-NA,” Intel’s Phillips said. “You don’t need a giant compute die if you’re doing it this way.”

Still, there is a throughput hit. For smaller dies without stitching, the throughput is 155 to 170 wph, according to ASML.

What’s missing
In high-NA, there are several other gaps, such as the mask technologies and resists.

In mask making, the process starts with a mask blank. An EUV mask blank consists of 40 to 50 alternating layers of silicon and molybdenum on a substrate, resulting in a multi-layer stack that is 250nm to 350nm thick. On top of this multi-layer stack, the mask blank also includes a ruthenium-based capping layer, followed by a tantalum absorber.

To help solve the 3D effects, the industry may require new and thinner absorber materials. “3D effects are even more pronounced with high-NA,” said Geoff Akiki, president of Hoya Blanks. “Therefore, thinner absorbers are more important. That’s driving the push to new materials for reduced 3D effects.”

That doesn’t appear to be a roadblock. Today, the EUV mask production tools are also in place, including actinic mask inspection systems and multi-beam mask writers. What’s missing is the EUV pellicle.

Like photomasks, resists are critical in lithography. For EUV, the industry uses chemically amplified resists (CARs) with metal oxide resists in the works.

“Today’s resists for EUV are based on chemical amplification,” Lam’s Wise said. “An EUV photon (92eV) interacts with resist and forms a primary (~80eV) electron, which in turn collides and causes a cascade of secondary electrons at much lower energy that are captured by photoacids (PAG). Each one of these steps requires a finite distance, for example the PAG is spaced several nanometers apart, and the electrons tend to move randomly a few nanometers before being captured. This variation in spacing is termed ‘resist blur’ and fundamentally limits the resolution. The industry consensus seems to be that chemically amplified resist blur limits resolution below 30nm pitch.”

So for high-NA EUV, the industry will likely need resists beyond CARs. “Materials will be challenged to the limit,” Brewer Science’s Guerrero said. “Some say chemical amplified resists will not have the resolving power. With the decrease in focus at higher NA, the resist thickness will drop more. This means that there will be very little resist to have good contrast and high quality images. With lower contrast, roughness will be magnified.”

In a recent paper, ASML and Paul Scherrer Institute evaluated the performance of various resists for high-NA EUV. Based on the work, the inorganic resist showed the best performance (11nm half-pitch resolution) with low LER and a 67mJ/cm2 dose. Resists are still a work in progress.

Breakthroughs in resists and other technologies for high-NA are required. The industry is working on them, but there are several unknowns here.

In parallel, chipmakers are working on different architectures that circumvent chip scaling, such as advanced packaging. It’s good to have backup plans, just in case high-NA is delayed or falters.

Related Stories

Single Vs. Multi-Patterning EUV

Extending EUV Beyond 3nm


guest says:

It looks like non-EUV self-aligned multi-patterning will be cheaper than EUV. With stochastics and resist blur, the shorter wavelength is not helping anymore.

William Marx, former engineer on Cymer EUV project. says:

Litho engineers and resist specialists tend td to be pretty smart, plus there is lots of money in play and a growing knowledge base for EUV litho. I would bet on hi NA EUV.

Paul Derks says:

Very nice article and spot on analysis

High-NA Integration Architect says:

There is an incorrect statement about the number of mirrors in the ILLU: “EUV light goes through a programmable illuminator, where photons bounce off 10 multi-layer mirrors.” This is incorrect – there are only 3 mirrors in the the Low-NA (NXE) ILLU. The confusion probably starts from the total number or mirrors in the system: there is the collector (mirror) in the source, 3 in the ILLU, and 6 in the POB, totaling to 10 mirrors from the droplet to the wafer, not counting the reticle (which is technically a mirror). This is all public information. As I’m not sure what is public for High-NA (EXE) will keep quiet on that. Greetings from Veldhoven.

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