中文 English

What Is An xPU?


Almost every day there is an announcement about a new processor architecture, and it is given a three-letter acronym — TPU, IPU, NPU. But what really distinguishes them? Are there really that many unique processor architectures, or is something else happening? In 2018, John L. Hennessy and David A. Patterson delivered the Turing lecture entitled, "A New Golden Age for Computer Architecture... » read more

Changing Server Architectures In The Data Center


Data centers are undergoing a fundamental shift to boost server utilization and improve efficiency, optimizing architectures so available compute resources can be leveraged wherever they are needed. Traditionally, data centers were built with racks of servers, each server providing computing, memory, interconnect, and possibly acceleration resources. But when a server is selected, some of th... » read more

HBM3: Big Impact On Chip Design


An insatiable demand for bandwidth in everything from high-performance computing to AI training, gaming, and automotive applications is fueling the development of the next generation of high-bandwidth memory. HBM3 will bring a 2X bump in bandwidth and capacity per stack, as well as some other benefits. What was once considered a "slow and wide" memory technology to reduce signal traffic dela... » read more

Software-Hardware Co-Design Becomes Real


For the past 20 years, the industry has sought to deploy hardware/software co-design concepts. While it is making progress, software/hardware co-design appears to have a much brighter future. In order to understand the distinction between the two approaches, it is important to define some of the basics. Hardware/software co-design is essentially a bottom-up process, where hardware is deve... » read more

Vector Runahead


Abstract: "The memory wall places a significant limit on performance for many modern workloads. These applications feature complex chains of dependent, indirect memory accesses, which cannot be picked up by even the most advanced microarchitectural prefetchers. The result is that current out-of-order superscalar processors spend the majority of their time stalled. While it is possible to bui... » read more

Optimize Physical Verification Cost Of Ownership With Elastic CPU Management


For physical verification, advanced process technology nodes create implementation challenges. Design sizes have gotten larger and required rules from foundries have become more numerous in count (thousands) and more complex (hundreds of discrete steps). For these reasons, physical verification tools have been able to span these jobs not only across multiple CPUs on a single physical compute ho... » read more

CEO Outlook: More Data, More Integration, Same Deadlines


Experts at the Table: Semiconductor Engineering sat down to discuss the future of chip design and EDA tools with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; and Babak Taheri, CEO of Silvaco. What ... » read more

Tradeoffs To Improve Performance, Lower Power


Generic chips are no longer acceptable in competitive markets, and the trend is growing as designs become increasingly heterogeneous and targeted to specific workloads and applications. From the edge to the cloud, including everything from vehicles, smartphones, to commercial and industrial machinery, the trend increasingly is on maximizing performance using the least amount of energy. This ... » read more

Von Neumann Is Struggling


In an era dominated by machine learning, the von Neumann architecture is struggling to stay relevant. The world has changed from being control-centric to one that is data-centric, pushing processor architectures to evolve. Venture money is flooding into domain-specific architectures (DSA), but traditional processors also are evolving. For many markets, they continue to provide an effective s... » read more

Powering The Edge: Driving Optimal Performance With Ethos-N77 Processor


Repurposing a CPU, GPU, or DSP is an easy way to add ML capabilities to an edge device. However, where responsiveness or power efficiency is critical, a dedicated Neural Processing Unit (NPU) may be the best solution. In this paper, we describe how the Arm Ethos-N77 NPU delivers optimal performance. Click here to immediately download the paper. » read more

← Older posts