EUV’s Uncertain Future

Litho tech has finally arrived after years of delays and billions of dollars in investments. Now the question is who still needs it.


The ground appears to be solidifying under EUV. Intel announced this week it is reducing its stake in ASML to less than 3%, the second such move in a year. Apparently ASML no longer needs outside help.

According to the company’s earnings report, ASML turned in net sales of €2.776 billion, a slight increase over the €2.447 billion (GAAP) the company reported in Q3 and way up over the €1.814 billion reported in Q3 2017. In short, EUV revenues are growing.

That success follows a long, twisty, and painfully slow development path. EUV is a marvel of engineering and scientific achievement that has been under development for decades. It was first expected to be used somewhere around 45nm (there was even talk of rolling it out at 65nm), which would have sidestepped the need for both immersion lithography and multi-patterning. But just as it appeared that the technology was making real progress—and as multi-patterning was becoming really difficult for Metal 0 and Metal 1—ASML began struggling.

Having put all of their eggs in one basket, Intel, TSMC and Samsung agreed to invest €1.38 billion into ASML in July 2012 under what was called the Customer Co-Investment Program. In simple terms, it was a bailout, and those investors have been reducing their stakes as the technology has progressed. Both Samsung and Intel cut their stakes in ASML in September 2017. Intel slashed its stake from 15% to 7.6%, and has made additional cuts since then, including one this week.

Now, after literally decades of development, EUV is finally real. There are still some pieces missing, such as a pellicle, and the power supply still needs improvements, but the technology works well enough that Samsung is using it commercially today at 7nm, and TSMC announced that it has taped out its first design using EUV in risk production. Intel remains silent, having delayed its 10nm chips until next year. (Intel’s 10nm is roughly the same as 7nm for TSMC and Samsung.)

What’s not entirely clear, though, is just how well EUV will fare over time. At this point, there are only two foundries using EUV, and at Samsung and TSMC’s version of 5nm, double patterning will still be required. ASML has plans to extend EUV at least two or three nodes beyond that using high-NA (numerical aperture) technology, but that introduces yet another technology with no clear cost/benefit formula at a time when the power/performance benefits of continued device scaling are dropping significantly.

For most chipmakers, there is better return on architectural and micro-architectural changes than from shrinking feature sizes. Below 5nm, the real value in feature shrinks is the lower voltage, not performance increases. In fact, 20% improvements in performance may be optimistic, while new architectures and different packaging options could provide bigger boosts in performance for far lower NRE. That’s especially important for applications outside of smartphones, where the cost cannot be amortized over billions of units or built into the overall rising price of the end device.

Still, the market for smartphones is flattening. Softbank COO Marcelo Claure estimates there will be 1 trillion connected things over the next couple decades, representing $11 trillion in economic value. For the chip industry, this translates into enormous opportunity in building the infrastructure to connect all of those things and manage the data generated by tens of billions of sensors. Only a fraction of that business will be tied to the latest process node. In fact, a lot of it will happen at older nodes using 200mm wafers.

That leaves continued investment in lithography and very expensive manufacturing process technology with increasingly uncertain future demand. This is a very high-stakes game being played by a shrinking number of companies, and the ante continues to rise. GlobalFoundries already has announced it will not pursue 7nm, and it’s not clear the industry can handle another dropout.

At a time when new markets are emerging everywhere, it’s still not obvious how all of the pieces will fit together. Given recent startup investments and M&A activity, however, there appears to be far less interest in lithography than in new opportunities where process size is less important than overall power and performance. That could change if prices for developing chips at advanced processes drops enough. But that’s a big “if,” and it has to be keeping a lot of people awake at night wondering which way the pendulum will swing.

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Rick de la harta says:

Any understanding what is the timeline of any EUV actinic mask inspection tool?

Mike Delfino says:

Making some valid points, however the co-investment program was to secure funding for 450mm development that was driven by these customers only and has since been shelved. More likely Intel is selling its stake (with tons of profit) to plug some leaks in their organization

Mark LaPedus says:

Lasertec says that the EUV actinic mask inspection tool is still under development. It may ship this year. Resists, uptime and pellicle are the big problems

cyw60 says:

Nope, actinic mask inspection program is not shipping this year or next. Intel funded Lasertec last year (order announced Sept 2017), and they said it’s a 2 year+ development program followed by commercial tools shipments thereafter. Most likely a 2020 shipment time to coincide with pellicle use at TSMC 5nm. It’s possible some R&D tools begin showing up next year, but commercially likely much later. At least this is what Lasertec is saying

Michel says:

This title is quite missing the point. DUV multiple patterning is the one that has an uncertain future. TSMC is taping out the first generation of EUV chips. ASML is selling 10’s of EUV systems per year. EUV is already present.

resistion says:

Most layers still multipatterned at TSMC and Samsung, so the EUV reduction is overshadowed. The EUV shipments are already falling short of target.

Tanj says:

EUV has a future, but run the numbers. If goals are reached 1 machine will process a million wafers in a year (sustained average 120 wph). The advertised processes require at least 5 layers with EUV, so, 5 machines. Half of ASML’s production this year? TSMC alone will need 50 to 100 machines if 7nm is to become a workhorse, which will take many years both of production and refinement. For now it will be used for hero devices in large volume. At around 400 devices per wafer, those 5 machines would just about satisfy demand for someone like Apple.

Meanwhile, there will be a lot of refinement and use of processes without EUV. The landscape here is diversity, not all-eggs-in-one-basket.

resistion says:

Presently it’s about 1000-1500 wafers per day. There is still no pellicle and the stochastics are already a showstopper essentially.

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