Stacked Nanosheets And Forksheet FETs

Next-gen transistors will continue using silicon, but gate structures and processes will change.


What comes next after gate-all-around FETs is still being worked out, but it likely will involve some version of stacked nanosheets.

The design of advanced transistors is a tradeoff. On one hand, it takes less gate capacitance to control a thin channel. On the other hand, thin channels can’t carry as much drive current.

Stacked nanosheet designs seek to reconcile these two objectives by using several thin channels, each with its own gate electrodes. Though these devices are similar to finFETs, the stacked nanosheet process flow introduces several new modules, and presentations at June’s VLSI Technology Symposium considered how these new modules contribute to overall performance.

Nanosheet transistors typically start with a Si/SiGe heterostructure, with as many layer pairs as the finished device will have channels. This structure could serve as a starting point for either silicon or silicon-germanium channels.

Naoto Horiguchi, director of Imec’s CMOS logic device technology program, explained that while SiGe’s higher mobility ultimately may be required, most stacked nanosheet transistor demonstrations currently use the SiGe as a sacrificial layer. Typically, the silicon nanosheets are undoped. The work function of the gate metal defines the threshold voltage.

The interface between the silicon and silicon germanium layers defines the ultimate channel quality. Kevin Moraes, vice president at Applied Materials, emphasized the need for abrupt, atomically flat transitions. To minimize parasitics and high frequency losses in the finished device, the spacing between layers should be as small as possible, within the limits of manufacturability.

Fig. 1: Stacked nanosheet process flow. Source: Imec

Fig. 1: Stacked nanosheet process flow. Source: Imec

The next few steps proceed as in a typical finFET process, with fin patterning, isolation, and formation of a dummy gate. Then, prior to deposition of the epitaxial source and drain layers, an inner spacer defines the gap between the gate and the source/drain. Inner spacer formation involves selectively etching a recess in the SiGe layer, then filling it with dielectric material.

Like the spacer in planar transistors, the dimensions of the inner spacer are critical because that spacer aligns the gate and helps to control leakage and parasitic capacitances. It also plays an important structural role — source/drain epitaxy is followed by a channel release etch, removing the SiGe and leaving the channel layers supported only at the edges.

Khwang-Sun Lee and Jun-Young Park of Korea’s Chungbuk National University showed that the profile and mechanical properties of the inner spacer can make the whole structure more or less likely to deform. Excessive strain poses reliability concerns, as well as affecting carrier mobility and other device parameters.

After the channel release etch, first a gate dielectric and then gate metal fills the gap. The space between nanosheets needs to be large enough to allow for removal of etch residue, deposition, and removal of a sacrificial gate, and finally deposition of the gate dielectric and gate electrode.

In a replacement gate process, half the devices are masked while sacrificial gate metal is removed from the other half. In a stacked nanosheet structure, though, the mask for this step must protect not just the surface, but also the exposed side of the stack. The minimum spacing between N-type and P-type devices is limited by the ability of the lithography process to define this mask, and by the need to avoid undercutting the mask during the metal etch. Moreover, the etch process must be selective enough to prevent erosion of the mask edges, which would affect the gate dimensions.

The need to reduce standard cell height is helping to motivate the introduction of nanosheet designs. Defined by the metal pitch, the cell height establishes the maximum spacing between complementary N-type and P-type devices. The minimum gap between the two, in turn, defines the channel width and therefore the available drive current. The wider the trench fabricated in this step needs to be, the less space is left for current-carrying channel material.

This need to minimize N-P spacing motivates Imec’s “forksheet” device design. In an interview, Horiguchi explained that intentionally de-tuning the fin etch process allowed Imec to create a sub-20 nm gap between device fins. They filled this gap with a silicon nitride wall, which served as an insulator and etch stop between the N-type and P-type devices. Forksheet FETs had performance comparable to gate-all-around nanosheet reference devices on the same wafer, but with only a 17nm space between the N-type and P-type devices.

Fig. 2: N and P-type forksheet FET pair (left) and stacked nanosheet FET (right). Source: imec

Fig. 2: N and P-type forksheet FET pair (left) and stacked nanosheet FET (right). Source: imec

Forksheet FETs and other stacked nanosheet designs show that, despite the potential advantages of 2D semiconductors, silicon isn’t done yet.

Nudging 2D Semiconductors Forward
Stacked nanosheet transistors promise to extend silicon’s reign beyond the finFET era.
The Future Of Transistors And IC Architectures
The more compute power, the better. But what’s the best way to get there?
Thinner Channels With 2D Semiconductors
Research into new materials booms as the number of manufacturing challenges increases at future nodes.
The Increasingly Uneven Race To 3nm/2nm
An emphasis on customization, many more packaging options, and rising costs of scaling are changing dynamics across the industry.
Making Chips At 3nm And Beyond
Lots of new technologies, problems and uncertainty as device scaling continues.
Imec’s Plan For Continued Scaling
The path forward for EUV and the new transistor types needed to reach 1nm.

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