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Nudging 2D semiconductors forward

Stacked nanosheet transistors promise to extend silicon’s reign beyond the finFET era.


The buzz about 2D materials replacing silicon appears to be premature.

While 2D semiconductors have emerged as potential successors, it’s not clear when or even if that will happen. As Iuliana Radu, Imec’s director of quantum and exploratory computing observed, the “end” of silicon has been predicted many times before. It is not clear when 2D semiconductors will need to be ready.
In fact, comparing the 2D semiconductor results presented at the recent VLSI Symposium with the latest silicon nanosheet developments emphasizes just how far 2D materials have to go.

The best 2D semiconductor devices so far depend on layer transfer techniques. Growing a transition metal dichalcogenide (TMD) layer on a separate substrate allows the use of much higher temperatures than a pre-fabricated bottom gate could tolerate. As discussed previously, though, TMD films tend to grow from multiple nucleation sites, potentially with different orientations. Defects and grain boundaries form as the initial islands merge.

At this early stage, it’s hard to say what approach, or even what material, will ultimately prevail. Ravi Kanjolia, a technology fellow at EMD Electronics, pointed out that MOCVD and ALD, the two most commonly used deposition techniques, both have advantages and disadvantages. MOCVD tends to require higher deposition temperatures, but also can produce higher-purity material. On the other hand, the layer-by-layer growth of ALD films can use lower temperatures and may give better conformality.

In either case, adoption of a material in manufacturing depends on more than the fundamental material properties. Are the precursors for a proposed material manufacturable on a large scale? Are they stable enough to be handled and transported safely?

Of the chalcogens, Michael Miller, a member of technical staff managing EMD Electronics’s 2D materials programs, said that sulfur is the least reactive, followed by selenium, then tellurium. Sulfur is also several orders of magnitude more abundant than either tellurium or selenium.

Like silicon nanosheets, 2D nanosheets are expected to need multiple channel layers to carry enough current. Both direct deposition and layer transfer approaches will involve multiple process steps for each layer, each increasing the wafer cost. WS2 is attractive, Radu said, in part because it appears able to carry more current than MoS2, delivering the same total current with fewer device layers.

Chelsey Dorow and colleagues at Intel demonstrated selective CVD growth of WS2, using patterned WOx seeds to provide a template. Selective growth may offer a simpler route to device-quality material than attempting to deposit a continuous film over the full surface of a 300 mm wafer.

According to Chih-Pin Lin and colleagues at Taiwan’s National Yang Ming Chiao Tung University, solid phase epitaxy may provide an alternative to vapor deposition methods. In multilayer stacks, the need to protect one layer while depositing the next adds complexity and reduces the available process space. This group eliminated the issue by co-sputtering the metal and chalcogen, followed by a cap layer. After depositing as many of these “sandwiches” as desired, they annealed the entire stack at once.

Work presented at the conference focused on MoTe2 material, which is appealing because formation of a second crystal layer is less energetically favorable than in other TMDs. They expect the approach to work for other materials as well.

The next step after successful material deposition is doping. While the polarity of the injected current can be used to control the polarity of 2D devices, practical circuits will need to use doping, the contact metal, or a combination of both. The Intel group produced NMOS and PMOS WSe devices in the same process by using Al2O3 as the gate dielectric for NMOS, and HfO2 for PMOS.

Finally, contacts are a third key requirement for practical transistors. Precisely because 2D materials have no dangling surface bonds, standard contact methods like creating a conducting alloy (such as a metal silicide) between the semiconductor and the metal are not available. Rather, as a recent report by MIT’s Pin-Chun Shen and colleagues explained, the work function of the metal perturbs the semiconductor band structure. These metal-induced gap states (MIGS) cause Fermi level pinning and introduce an energy barrier between the metal and the semiconductor.

This group — a collaboration between MIT, TSMC, and several other universities — deposited bismuth, a semimetal, at the interface. By occupying the valence band states at the interface, the bismuth prevented MIGS formation, leading to a low resistance contact. While Radu said this is an important result, the melting temperature of bismuth is only 271ºC. A manufacturable process probably will need to use a bismuth alloy instead.

Put in perspective, 2D semiconductors have a long way to go. While silicon nanosheets are optimizing potential manufacturing processes, TMD semiconductor researchers are still answering basic questions about film fabrication and contact formation. As shrinking transistors demand thinner and thinner channels, though, the opportunity for 2D materials eventually will come.

Stacked Nanosheets And Forksheet FETs
Next-gen transistors will continue using silicon, but gate structures and processes will change.
Thinner Channels With 2D Semiconductors
Research into new materials booms as the number of manufacturing challenges increases at future nodes.
The Future Of Transistors And IC Architectures
The more compute power, the better. But what’s the best way to get there?
The Increasingly Uneven Race To 3nm/2nm
An emphasis on customization, many more packaging options, and rising costs of scaling are changing dynamics across the industry.
Imec’s Plan For Continued Scaling
The path forward for EUV and the new transistor types needed to reach 1nm.


Greg Yeric says:

There would need to be a radical improvement in subthreshold slope, concurrent with a radical improvement in variability, without sacrificing contact resistance, to make any new electrostatically driven new MOS material viable compared to silicon. 2D semiconductors may get there, and they may also help in reducing the height profile to help reduce parasitic RC, but without the surmounting of these challenges in parallel, we then need to find a new type of device that does not require charging and discharging nodes to 0.5V.

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