Three Steps To Low Power Coverage Closure

Verifying the complex interactions between power elements at a high abstraction level.


By Awashesh Kumar and Madhur Bhargava

Low-power design and verification is becoming more complex. Yet it is critical that all power elements are verified, and it is even more important to verify the complex interactions between these elements at a high abstraction level.

However, power-aware coverage closure is difficult to attain and complex by nature. Existing low-power coverage methodologies are error prone and highly time consuming. A faster and more direct approach is needed.

It is a challenge to capture the coverage information of UPF objects and power states for the following reasons:

  • Power states are written in an abstract manner in UPF
  • There is no pre-defined coverage metric to capture power states and their transitions
  • The Unified Coverage Interoperability Standard (UCIS) defines various standard metrics related to coverage items; however, it does not provide any metric to capture power intent

In this article we present a three-step methodology using UPF 3.0 HDL package functions with SystemVerilog coverage constructs to achieve coverage of key design failure scenarios found in low power designs. Using this methodology, coverage closure can be achieved in a much more efficient way, thereby significantly saving verification effort and time.

A random, directed low power coverage methodology
UPF 3.0 HDL functions can be combined with SystemVerilog functional coverage constructs, such as covergroups and coverpoints, to create an efficient and directed low power coverage methodology. This low power coverage methodology enables users to write fast and reliable low power coverage infrastructures and perform random and directed low power verification. Random because testing scenarios can be developed by generic scripts. Directed because it can cover very specific scenarios.

The proposed coverage methodology involves getting the handle of a low-power object in HDL using an information model and querying the properties of that object. These properties are then passed to the coverage module as port mapping. The coverage module has the covergroups and coverbins to represent the coverage data of low-power strategies of that domain, or dynamic information (such as the current power state of the domain) can be queried in the testbench.

Figure 1: UPF Information Model

This methodology has three steps:

1. Low power object handle: The first step is to get the handle of the low power This can be achieved by using the HDL package function “upf_get_handle_by_name”. A property which is a list can be iterated through the HDL access function “upf_iter_get_next”. The following SystemVerilog code illustrates the usage of these basic functions to access low power objects.

upfHandleT pd = upf_get_handle_by_name("/tb/dut/pd")

upfHandleT pd_state_list = upf_query_object_properties(pd, UPF_PD_STATES)

upfHandleT pd_state = upf_iter_get_next(pd_state_list);

2. Dynamic property(value) of low power object: In this step, we get the dynamic value of the property of interest. For example, a user might be interested in knowing the current power state of a power domain in order to check the state of this power domain against the current power state of some other power Also, a user may use UPF 3.0 continuous access HDL package functions to continually monitor the power state of the power domain and may use assertions for anomalies and other scenarios of interest.

upfPdSsObjT pd_hdl;

upf_create_object_mirror(“/tb/dut/pd”, “pd”);

upfPowerStateObjT pwr_state = pd.current_state;

upfHandleT pd_name = upf_query_object_properties(pd.handle, UPF_NAME);

upfHandleT state_name = upf_query_object_properties(pwr_state.handle, UPF_NAME);

[email protected](pd)

$display( "Power domain %s, is in Power State: %s, upf_get_value_str(pd_name), upf_get_value_str(state_name));

3. Coverage details: Once we have the handle of a low-power object and its dynamic value, the information is passed to a coverage The coverage module can be modeled in SystemVerilog and compiled together with the design. This module is instantiated in the testbench. The low-power object extracted from the information model and its dynamic properties are passed in the interface of this coverage instance. Users can instantiate as many coverage instances as required. Coverage properties (covergroups/coverpoints) are defined inside this coverage module to calculate the coverage metrics.

module covIsoModule (int dynamicValue, string objName) reg cov_clk = 0;

covergroup LOW_POWER_STATE_COVERAGE(posedge @cov_clk)
     ACTIVE_LEVEL: coverpoint isovalue { bins ACTIVE = 1; }
     ACTIVE_LOW: coverpoint isovalue { bins ACTIVE = 0; }




Verification engineers can use the proposed verification approach to achieve an early low-power coverage closure. It is possible to do a directed scenario testing using this methodology. For example, users can write a custom assertion or property to check if two domains should be in a mutually exclusive state by using a UPF 3.0 information model immediate read access function. Since the methodology relies on UPF constructs, it is consistent and usable across different vendor tools. Even without detailed knowledge of complex UPF constructs and semantics, verification engineers can write various directed verification scenarios to achieve low-power coverage closure. The proposed approach can be easily scaled to bigger and more complex low power design scenarios. Cross coverage of power states can be easily mapped to this approach. This methodology will help achieve verification closure in significantly less time.

To learn more, checkout our whitepaper, Random Directed Low Power Coverage Methodology.

Madhur Bhargava is a member of the consulting staff with Mentor, a Siemens Business. Bhargava has more than 8 years of experience in low power verification and technology. He holds a bachelor’s degree in Electronics and communication engineering from Delhi College of Engineering, India. He is also an active member in the UPF working group.

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