Dissolving The Barriers In Multi-Substrate 3D-IC Assembly Design

Ensuring the intended connectivity of the die, silicon interposer, and organic substrate.


Advanced packaging continues to promise improved form factor, cost, performance, and functionality compared to the traditional transistor scaling on SoCs. This is done by integrating multiple dies on top of a substrate (organic or silicon). Besides multiple dies, multiple substrates can typically exist in a 3D-IC assembly. In this case, the benefits of advanced packaging are taken to a whole new level since the designer can leverage the advantages of different substrate manufacturing methods.

Including a silicon interposer as one of the substrates in the assembly is becoming more popular than ever since it enables slicing a big SoC into chiplets and connecting them externally through the interposer.

Fig. 1: 2.5D-IC assembly that includes two substrates (silicon interposer + organic package).

In terms of EDA physical verification, designers must ensure that the 3D-IC assembly is connected as expected compared to the golden design intent (captured as a system-level netlist). However, capturing a system-level netlist can be a challenge in the case of multiple substrates since each substrate usually requires a different design team, methodology, and/or format.

Capturing system-level connectivity

For 3D-IC assembly purposes, the intended connectivity of the die, silicon interposer, and organic substrate must be captured. The silicon interposer is usually owned by an IC design team that uses advanced SoC design EDA tools and formats. Meanwhile, the organic substrate is usually owned by the package design team that uses traditional package design EDA tools and formats.

Although the organic substrate is usually captured as a spreadsheet, the silicon interposer connectivity can be captured in many ways—among the most popular ways is in a Verilog netlist format. Thus, an EDA, system-level planning cockpit that can consume different connectivity formats is required.

Executing assembly verification

In the case of a typical silicon interposer (one substrate), the physical verification of an individual die is not enough; two more steps are required for full assembly verification:

  1. Interposer design rule checks (DRC) and layout versus schematic (LVS) checks
  2. Die alignment and connectivity to the interposer

Although interposer DRC and LVS can be delivered by the foundry, die alignment and connectivity to the interposer cannot since the die’s location and orientation can change from one 3D-IC project to another.

In the case of multiple substrates (from multiple manufacturers), the challenge gets even trickier since no single manufacturer can provide a full assembly verification runset. Hence, it falls to the system-level designer to create this full system runset. Ideally, this should be automated so that it doesn’t add a burden to the designer to develop EDA PDKs.

Xpedition Substrate Integrator (xSI) is the Siemens EDA offering for system-level connectivity capture and management. It is a single EDA platform that allows the import of different die, interposer, package, and PCB abstracts. In terms of formats, the user can import CSV, text files, LEF/DEF, ODB++, and many more.

Fig. 2: Example of an interposer + package floorplan in the xSI GUI.

Recently, xSI added support for the Verilog netlist format on import. This is very useful when importing silicon interposer connectivity, as stated above.

xSI also offers a plug-in that can automatically generate the 3D-IC assembly verification runset using Calibre 3DSTACK (full assembly descriptions and comprehensive assembly checks) along with a system source netlist. This approach is agnostic to the different die technology nodes, the different substrates involved in the assembly, and the different manufacturing vendors.

Multi-substrate 3D-IC assemblies are already in use by many technology leaders. Siemens has responded to the discontinuity introduced by such advanced packaging technologies by offering a state-of-the-art tool set that accommodates the challenges of system-level connectivity planning and verification.

A fuller treatment on this topic is presented in the Siemens white paper, System-Level Connectivity Management and Verification of 3D IC Heterogeneous Assemblies.

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