Physical Verification Of FinFETs And Fully Depleted SOI

Dealing with physical effects below 20nm requires new architectures, new methodologies and new tools.

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It has become very difficult to effectively shrink traditional bulk planar transistors below 20nm due to physical effects that become dominant in very short conduction channels. The major impediment is an unacceptable rise in power consumption due to significant leakage currents. New transistor architectures are being adopted that offer a solution for these short-channel effects and allow transistors to continue shrinking below 20nm. One of these new architectures is the three-dimensional finFET transistor and the other is the fully depleted silicon-on-insulator transistor. Both solutions are technically viable, both have proven production level success, and both have the backing of major semiconductor companies. These alternative transistor architectures will require adjustments in design methodologies and EDA tools but this examination shows that all required physical verification tool capabilities are in place and ready for production use.

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