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Piecing Together Chiplets


Several companies are implementing the chiplet model as a means to develop next-generation 3D-like chip designs, but this methodology still has a long way to go before it becomes mainstream for the rest of the industry. It takes several pieces to bring up a 3D chip design using the chiplet model. A few large players have the pieces, though most are proprietary. Others are missing some key co... » read more

Bumps Vs. Hybrid Bonding For Advanced Packaging


Advanced packaging continues to gain steam, but now customers must decide whether to design their next high-end packages using existing interconnect schemes or move to a next-generation, higher-density technology called copper hybrid bonding. The decision is far from simple, and in some cases both technologies may be used. Each technology adds new capabilities in next-generation advanced pac... » read more

Fan-Out Packaging Options Grow


Chipmakers, OSATs and R&D organizations are developing the next wave of fan-out packages for a range of applications, but sorting out the new options and finding the right solution is proving to be a challenge. Fan-out is a way to assemble one or more dies in an advanced package, enabling chips with better performance and more I/Os for applications like computing, IoT, networking and sma... » read more

Thermal Floorplanning For Chips


Heat management is becoming crucial to an increasing number of chips, and it's one of a growing number of interconnected factors that must be considered throughout the entire development flow. At the same time, design requirements are exacerbating thermal problems. Those designs either have to increase margins or become more intelligent about the way heat is generated, distributed, and dissi... » read more

Advanced Packaging’s Next Wave


Packaging houses are readying the next wave of advanced packages, enabling new system-level chip designs for a range of applications. These advanced packages involve a range of technologies, such as 2.5D/3D, chiplets, fan-out and system-in-package (SiP). Each of these, in turn, offers an array of options for assembling and integrating complex dies in an advanced package, providing chip custo... » read more

HBM Takes On A Much Bigger Role


High-bandwidth memory is getting faster and showing up in more designs, but this stacked DRAM technology may play a much bigger role as a gateway for both chiplet-based SoCs and true 3D designs. HBM increasingly is being viewed as a way of pushing heterogenous distributed processing to a completely different level. Once viewed as an expensive technology that only could be utilized in the hig... » read more

Making Chip Packaging More Reliable


Packaging houses are readying the next wave of IC packages, but these products must prove to be reliable before they are incorporated into systems. These packages involve several advanced technologies, such as 2.5D/3D, chiplets and fan-out, but vendors also are working on new versions of more mature package types, like wirebond and leadframe technologies. As with previous products, packaging... » read more

Many Chiplet Challenges Ahead


Over the past couple of months, Semiconductor Engineering has looked into several aspects of 2.5D and 3D system design, the emerging standards and steps that the industry is taking to make this more broadly adopted. This final article focuses on the potential problems and what remains to be addressed before the technology becomes sustainable to the mass market. Advanced packaging is seen as ... » read more

What Goes Wrong In Advanced Packages


Advanced packaging may be the best way forward for massive improvements in performance, lower power, and different form factors, but it adds a whole new set of issues that were much better understood when Moore's Law and the ITRS roadmap created a semi-standardized path forward for the chip industry. Different advanced packaging options — system-in-package, fan-outs, 2.5D, 3D-IC — have a... » read more

The Future Of Transistors And IC Architectures


Semiconductor Engineering sat down to discuss chip scaling, transistors, new architectures, and packaging with Jerry Chen, head of global business development for manufacturing & industrials at Nvidia; David Fried, vice president of computational products at Lam Research; Mark Shirey, vice president of marketing and applications at KLA; and Aki Fujimura, CEO of D2S. What follows are excerpt... » read more

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