Building Tomorrow’s Electronics Piece By Piece

Standardized approaches will be needed to ensure that all chiplets work seamlessly together as a unified system.


The semiconductor landscape is undergoing a seismic shift as the demand for more powerful and energy-efficient electronic devices reaches new heights. In a recent panel discussion at CadenceLIVE Europe, featuring luminaries such as Kevork Kechichian from Arm, Paul Cunningham from Cadence, Norbert Schuhmann from Fraunhofer, Trent Uehling from NXP, Davide Rossi from the University of Bologna, and moderated by David Hardisty, Cadence, the spotlight was on 3D-IC chiplets—a groundbreaking technology poised to redefine the future of electronics.

As the limitations of Moore’s Law and traditional 2D chip architectures loom large, experts from academia and industry converged to explore the promises of 3D-IC chiplets integration. This dynamic discussion covered everything from design considerations and manufacturing challenges to the transformative impact on market trends and performance enhancements.

Why the buzz around chiplets?

Kevork shed light on the significance of chiplets in manufacturing, emphasizing the cost considerations and scalability that make chiplets a game-changer. With decades of industry exploration, chiplets have evolved to become essential, offering a flexible and efficient solution for various compute subsystems. Paul echoed Kevork’s sentiments, emphasizing the myriad benefits of chiplets, including reduced latency, increased memory bandwidth, and overall efficiency. The potential to revolutionize the industry became evident as chiplets opened doors to reusing soft IP on a whole new level. Norbert introduced the concept of using specific or complex chiplet designs on interposers to cater to the diverse needs of products and technologies. This approach, avoiding the monolithic design of everything on a single chip, provides opportunities for dedicated needs in analog, RF, compute, and power.

How is heterogeneous integration enabling the chip adoption trend?

Trent explained the realm of heterogeneous integration, emphasizing its historical use in combining analog and digital technologies. He highlighted the increasing importance of RF power and latency memory in heterogeneous packaging, signaling a shift in the industry’s approach to adopting chiplet interfaces. He mentioned that a package’s complexity depends on the interface type used, and the more complex the package, the more complex the interface needs to be. In the past, simple interfaces were used, but with increasing package complexity, interfaces are becoming more complex as well.

What are the risks and rewards of chiplets?

When it comes to risk, Trent acknowledged the challenges associated with designing standalone chiplets. Integrating individual, standalone chiplets into a complete functional system requires careful consideration and presents several challenges. One primary concern is ensuring the chips’ quality and the tests they undergo. The industry is already considering this, but more work needs to be done to implement JTAG, NIST, and other essential factors on these chips and entire systems.

Another challenge is determining who takes ownership of the process when chiplets come from multiple suppliers. Ultimately, someone must take responsibility for the yield based on anticipated models of the entire system. Currently, the industry lacks a chiplet ecosystem that can integrate chiplets from multiple suppliers. This requires another paradigm shift regarding integration, much like what the automotive industry has gone through.

The issue of degradation is also a concern. If something isn’t functioning properly, how can it be recalled, especially if it only manifests at the system level? Standardized synthesis and testing approaches are needed to ensure that all chiplets work seamlessly together as a unified system, regardless of their source. In fact, the industry must work to implement standardized approaches to overcome the challenges associated with the integration of individual, standalone chiplets. The success of this approach will depend on developing a robust chiplet ecosystem that can integrate chiplets from different suppliers into a cohesive system. This will require collaboration and consensus-building across the industry to establish standards and best practices that enable the efficient and effective integration of chiplets.

Which industries, or verticals, will benefit most from chiplets in the near term?

Trent predicted that while the automotive industry faces challenges, IoT and edge computing will be the early adopters of chiplet technology, leveraging its benefits for existing multicore applications. Davide underscored the potential benefits of chiplets in IoT, wearable technology, high-performance computing, and the automotive sector. He emphasized the need for a standardized way to interface with different technologies to unlock the full potential of chiplets. Paul envisioned hyperscalers adopting chiplet-based approaches for quick silicon releases, foreseeing a standardized chiplet and diverse 3D-IC applications in data centers, automotive control units, and IoT. Kevork agreed that all markets could benefit from chiplet technology, but certain industries would have more incentives due to the high costs involved. He emphasized the need for integrators in the market to assemble chiplets efficiently.

Where do you see the vision and importance of chiplets going forward?

Looking ahead, Kevork stressed the importance of standardization in an industry lacking consistency. He recognized the need for expertise and tools for pre-silicon analysis, envisioning standardization as the key to accelerating the industry’s pace. Paul applauded the move towards standard interfaces like UCIe, enabling the seamless integration of memory dies. He foresaw diverse applications across high-performance computing, automotive control units, and IoT. Norbert highlighted challenges in chiplet standardization for communication and seamless interposer design flow. Despite these hurdles, he saw an opportunity for diverse chips to work together.

Trent drew parallels between the historical trajectory of high-performance computing driving silicon advances and the future role of chiplets. He stressed the importance of scalability to avoid unnecessary overhead. Davide emphasized the collaborative potential between academia and industry in developing chiplet technology. He saw chiplets as a promising opportunity for industry-academia collaboration and student training.

In conclusion, the panel discussion unraveled the intricate world of 3D-IC chiplets, showcasing diverse perspectives and insights from industry leaders. As chiplets continue to gain momentum, the journey towards standardization, seamless integration, and unlocking their full potential promises a revolutionary era in semiconductor technology.

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