The need, challenges, and solutions for 3D-IC design and analysis.
As we approach the device scaling limitations at advanced nodes, the demand on compute performance and data transfer for hyperscale data center and AI designs is at an all-time high. Advanced systems-on-chip (SoCs) are reaching reticle size limits, and there has been a need to find innovative solutions to continue Moore’s law scaling and achieve performance improvements with reduced power. Stacking chips in the same package (3D) and a multi-chiplet system with silicon interposer on the same package (2.5D) are emerging as solutions of choice, which come with their own challenges. This white paper discusses the need, challenges, and solutions for 3D-IC design and analysis achieved with the Cadence Integrity 3D-IC platform, the industry’s first integrated solution for system planning, implementation, and system-level analysis. By getting early feedback from system-level analysis flows, 3D-IC designers can get the benefits of system-driven PPA and avoid overdesign of individual chiplets.
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