The Future Of Transistors And IC Architectures

By Mark LaPedus - 18 Mar, 2021 - Comments: 1

Semiconductor Engineering sat down to discuss chip scaling, transistors, new architectures, and packaging with Jerry Chen, head of global business development for manufacturing & industrials at Nvidia; David Fried, vice president of computational products at Lam Research; Mark Shirey, vice president of marketing and applications at KLA; and Aki Fujimura, CEO of D2S. What follows are excerpt... » read more

Adaptive Test Gains Ground

By Anne Meixner - 10 Nov, 2020 - Comments: 0

Not all devices get tested the same way anymore, and that’s a good thing. Quality, test costs, and yield have motivated product engineers to adopt test processes that fall under the umbrella of adaptive test, which uses test data to modify a subsequent test process. But to execute such techniques requires logistics that support analysis of data, as well as enabling changes to a test based ... » read more

Partitioning In 3D

By Katherine Derbyshire - 23 May, 2019 - Comments: 2

The best way to improve transistor density isn't necessarily to cram more of them onto a single die. Moore’s Law in its original form stated that device density doubles about every two years while cost remains constant. It relied on the observation that the cost of a processed silicon wafer remained constant regardless of the number of devices printed on it, which in turn depended on litho... » read more

22nm Process Technology

By Ed Sperling - 19 Jul, 2018 - Comments: 0

Jamie Shaeffer, senior director of product line management at GlobalFoundries, talks about how FD-SOI compares with bulk technologies, where it will be used and why, and future stacking options. https://youtu.be/2i7GJRxcNRs » read more

Tech Talk: MCU Memory Options

By Ed Sperling - 17 May, 2018 - Comments: 0

David Eggleston, vice president of embedded memory at GlobalFoundries, talks about the pros and cons of embedded non-volatile memory versus system in package. https://youtu.be/6KoQTFbFVCo » read more

How To Choose The Right Memory

By Ann Mutschler - 02 Apr, 2018 - Comments: 0

When it comes to designing memory, there is no such thing as one size fits all. And given the long list of memory types and usage scenarios, system architects must be absolutely clear on the system requirements for their application. A first decision is whether or not to put the memory on the logic die as part of the SoC, or keep it as off-chip memory. "The tradeoff between latency and th... » read more

Smaller, Faster, Cheaper—But Different

By Ed Sperling - 22 Mar, 2018 - Comments: 0

The old mantra of "smaller, faster, cheaper" has migrated from the chip level to the electronic system level, raising some interesting questions about where the real value is being generated. Smaller as it pertains to gate size, line widths and spaces, will continue in an almost straight line for at least the next decade. The ability to print three-dimensional features on a nanoscale using E... » read more

Will EUV Kill Multi-Patterning?

By David Abercrombie - 19 Jan, 2017 - Comments: 0

When I first began working on double-patterning (DP) tools back in late 2010, there was already talk that it might be a fruitless, or at a minimum, very short-lived project, as extreme ultraviolet (EUV) lithography was just around the corner and would make all multi-patterning (MP) obsolete. Well, as I begin my seventh year on this project, I can hear echoes of Mark Twain as clearly, the report... » read more

BEOL Issues At 10nm And 7nm (Part 1)

By Ed Sperling - 15 Dec, 2016 - Comments: 5

Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

Insider’s Guide To Fab Technology

By Mark LaPedus - 21 Apr, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss fab technology with Matt Paggi, vice president of advanced technology development at GlobalFoundries. What follows are excerpts of that conversation. SE: What’s driving demand for semiconductors today? Paggi: You are aware of what the worldwide semiconductor revenue growth is this year. There are peaks and valleys in the worldwide semiconduc... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.