Insider’s Guide To Fab Technology

GF discusses advanced processes and cost.


Semiconductor Engineering sat down to discuss fab technology with Matt Paggi, vice president of advanced technology development at GlobalFoundries. What follows are excerpts of that conversation.

SE: What’s driving demand for semiconductors today?

Paggi: You are aware of what the worldwide semiconductor revenue growth is this year. There are peaks and valleys in the worldwide semiconductor market year to year. In general, the application space will continue to explode. There is an expanding appetite for more processing through all these applications. You have the IoT. You also have the processing that is occurring from digital capture, video and imaging. All of these things are expanding the market.

SE: What are the considerations when moving to the next node?

Paggi: Everything is usually driven by economics. There needs to be a benefit in moving from 14nm to the next node.

SE: What else?

Paggi: There are three costs that are involved here that you have to factor in. Two are on the fab side. The newer nodes, in order to advance the technology, are more expensive. They require more lithography steps. They require more processing. And that adds a certain cost. Countering that cost is that the chips will get smaller. So there is a benefit. So if we normalize that on a per circuit basis, historically we want to get some improvement from generation to generation. Even though the absolute cost is going up, you shrink things enough and that compensates for it. And the net is a benefit. The third factor is that the design team aspect has to have some cost. There is a large investment going into a new node from a design perspective.

SE: Today, chipmakers are ramping up 16nm/14nm finFETs. Will foundry customers stay at 16nm/14nm for some time? Or will they move to the next nodes? How will this all play out?

Paggi: 14nm for the foundry industry is really the first-generation finFET. There has been a lot of work that had to be done to enable that first-generation finFET. Basically, it used the backend pitches and most of the density scaling of the 20nm node. And it primarily offered a performance advantage of the finFET. So, there is probably still a pent up demand to do something in a denser scale than 14nm, but the question is what?

SE: What makes more sense after 16nm/14nm? Is it 10nm or 7nm?

Paggi: The equation in simple form is this. Is the investment that you have to make in the design going to be overcome from the reduced cost per transistor? And in general, we are seeing that this financial equation is pretty tight for most customers at 10nm. 7nm, for most customers in most of the markets, appears to be a more favorable financial equation.

SE: Why does 7nm make more sense?

Paggi: When we look at the 7nm node, it offers a very compelling advantage over 14nm. There is an advantage in terms of density, performance and power, depending on how you want to take the transistor.

SE: When does GlobalFoundries plan to deploy 7nm?

Paggi: GlobalFoundries doesn’t want to discuss any dates right now.

SE: Generally, what will 7nm look like?

Paggi: It’s typical of a second-generation technology. There will be some material changes, probably in the middle-of-the-line to lower the resistances.

SE: It sounds like the 7nm node will make use of 193nm immersion lithography and multi-patterning. That sounds challenging. What about EUV at 7nm?

Paggi: We are investing heavily in EUV. We do believe in it as a future technology. It’s has had a long path. There is still a lot of work there. We’re not assuming it in our thinking about the initial part of 7nm.

SE: What about the channel materials for 7nm?

Paggi: All of the major players will be looking at silicon-germanium channels, particularly for the PFET. Whether those will be ready for the initial launches, or they show up as a subsequent kicker technology, it’s still to be seen. There are a lot of challenges with those materials.

SE: What about the back-end-of-the-line (BEOL)?

Paggi: There is new patterning that is coming in the backend. Some of the foundries have started this at 10nm. Certainty, by 7nm, there will be more extensive use of self-aligned patterning processes.

SE: Generally, will there be any demand for 7nm chips?

Paggi: If you step back and take the broader view, the market is not shrinking in terms of our desire for data. It is not shrinking for our desire for more processing, communications and transferring data. The applications are exploding around us. So, there is going to be a large need moving forward for 7nm. This will be a node that will be profitable over a long period of time.

SE: What will it cost to design a 7nm chip?

Paggi: There are no hard and fast rules. The chip density will increase. As I said earlier, it will cost you more too. The shrink benefit will outweigh the incremental cost increase coming from 14nm.

SE: Can you elaborate about IC design cost in general?

Paggi: Generally, semiconductors are getting more expensive to develop. Fewer and fewer companies can afford it. The same thing is happening from the fabless guys. It’s more and more expensive to do a design, because of the level of integration that is required, the complex IP that has to be developed, and the verification of this.

SE: Isn’t the soaring cost of IC design and manufacturing contributing to the ongoing consolidation in the industry?

Paggi: There has been a ton of consolidation in the industry. Look at the semiconductor side. And look at the fabless side. It takes large companies to afford the design work to leverage these chips. So there has been consolidation. But the net result is that you have fewer customers with bigger total volumes per part.

SE: What’s after 7nm?

Paggi: The industry hasn’t named it yet, but maybe it would be something like 5nm. The question is can we squeeze one more node out of a finFET device. Or does it require a different transistor? The question is can you come up with a manufacturing processes that would be at the right fin dimensions to support a 5nm technology. The question is can we control the finFET at those dimensions?

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