tag: TSVs

Powering AI At Scale: Why 3D-ICs Demand A New Approach To Power Integrity
By Muhammad Hassan - 07 May, 2026 - Comments: 0

By Muhammad Hassan and Sudarshan Deo The semiconductor industry is undergoing a fundamental transition. Performance scaling is no longer driven primarily by transistor density, but by advanced packaging—2.5D, 3D-ICs, chiplets, and heterogeneous integration. Fig. 1: 3D-IC and 2.5D structure. These architectures are essential to meeting the extreme performance and bandwidth demands... » read more

TSV Complexity Leads To Manufacturing Bottleneck
By Laura Peters - 22 Apr, 2026 - Comments: 1

Key Takeaways: Through-silicon vias are the biggest enabler of 3D chip stacking and chip-to-PCB connections through silicon interposers. The AI boom is causing HBM and advanced assembly shortages, straining the supply chain. Optimization around etch, fill and reveal help reduce TSV cost. Through-silicon vias (TSVs) provide essential interconnects between DRAM dies inside hig... » read more

Catching Critical Defects In TSVs And Stacked Chips
By Laura Peters - 10 Feb, 2026 - Comments: 0

Key Takeaways Variation is becoming a bigger problem in multi-die assemblies with TSVs and hybrid bonding. Multi-modal approaches are required to test these devices. AI plays a role in improving defect capture rate and distinguishing between yield-killing and false positives. New methods for interconnecting devices using through-silicon vias (TSVs) and hybrid bonding in stac... » read more

An Explosion In Interconnect Complexity
By Bryon Moyer - 22 Jan, 2026 - Comments: 0

For decades, electronics offered two levels of routing structure to manage signals that originate or terminate in an integrated circuit. Recently, that number has risen to five, and while it adds far more flexibility for structuring electronic equipment, it also brings greater complexity and ratchets up the number of design decisions needed to complete a project. This transition has been evo... » read more

What Is 3D-IC Technology? Fundamentals, Architecture, And Design Concepts
By Reela Samuel - 25 Nov, 2025 - Comments: 0

As process nodes continue to advance into the sub-micron era, the limitations of traditional scaling are becoming increasingly evident. Larger monolithic chips are facing challenges such as higher power density, routing congestion, and reduced yield. Three-dimensional integrated circuits (3D-IC) technology represents a breakthrough approach by stacking multiple dies vertically. This design red... » read more

HBM Leads The Way To Defect-Free Bumps
By Laura Peters - 11 Nov, 2025 - Comments: 0

High-bandwidth memory stands at the forefront of multiple technology developments as a critical enabler of AI, but it is one of the most difficult modules to manufacture. Leading HBM device makers and foundries must simultaneously handle multi-layer chip stacking, die warpage, and shorter product lifecycles that are shrinking from two years down to just one. But perhaps the most formidable c... » read more

Critical Factors For Storing Data In DRAM
By Ed Sperling - 27 Oct, 2025 - Comments: 0

DRAM is becoming more complicated to develop, and more difficult to manage inside AI data centers. In the past, latency, bandwidth, and capacity were the primary considerations. But as the amount of data that needs to be processed, moved, and stored continues to rise, a whole new set of factors is emerging. Steven Woo, fellow and distinguished inventor at Rambus, talks about latency under load,... » read more

On-Die And In-Package Interconnects: eBook
By Bryon Moyer - 28 Jul, 2025 - Comments: 0

We live in the Information Age, but if information cannot get to where it's intended to go, it does no good. And the way information gets from here to there is through interconnects. This report focuses on different interconnect structures, such as lines, vias, buses, and networks-on-chip, and how they’re constructed. As always, we consider the design, test, reliability, and security impli... » read more

The Other Side Of The Wafer: Transistor Channel Stress In Backside Power Delivery Networks
By Sam Sarkar - 17 Apr, 2025 - Comments: 0

As transistor scaling has moved to the angstrom era (18A, 14A, etc.), the issues of interconnect resistance (IR), IR drop, and power loss are becoming more severe. Traditionally, signal lines and power lines are fabricated on the same side of the wafer as the active device. But fabricating everything on one side of the wafer can create a shortage of space and resources at the interconnect la... » read more

Why Thin Film Measurements Matter
By Laura Peters - 08 Apr, 2025 - Comments: 0

Semiconductor devices are becoming thinner and more complex, making thin deposited films even harder to measure and control. With 3nm node devices in production and 2nm nodes ramping toward first-silicon, the importance of precise film measurement is only growing in significance as fabs seek to maintain the performance and reliability of leading-edge devices. Whether it’s the read and writ... » read more

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