Powering AI At Scale: Why 3D-ICs Demand A New Approach To Power Integrity

By Muhammad Hassan and Sudarshan Deo

The semiconductor industry is undergoing a fundamental transition. Performance scaling is no longer driven primarily by transistor density, but by advanced packaging—2.5D, 3D-ICs, chiplets, and heterogeneous integration.

Fig. 1: 3D-IC and 2.5D structure.

These architectures are essential to meeting the extreme performance and bandwidth demands of AI/ML and high‑performance computing. At the same time, they are radically increasing power delivery complexity, making power integrity (PI) one of the most critical constraints in modern system design.

What has changed most is not simply scale, but connectivity density: more dies, more power domains, more vertical interconnects, and dramatically higher current densities. This is forcing a shift from thinking of PI as a localized problem to a system‑level discipline.

Insight 1: Power delivery in 3D-ICs is fundamentally three‑dimensional

In traditional 2D SoCs, power delivery networks were largely planar, with well‑understood horizontal current flow and relatively localized noise behavior. In contrast, 3D-ICs introduce vertically stacked power paths spanning multiple dies, interposers, micro‑bumps, through silicon vias (TSV), and package planes.

This architectural shift creates new technical challenges:

• Vertical current crowding, where multiple dies draw current through shared TSVs and micro‑bump structures
• Cross‑die electrical coupling, allowing noise generated in one die to propagate vertically into others
• Shared return paths, which amplify L·di/dt noise and ground bounce

As AI workloads demand higher instantaneous current with shrinking voltage margins, power integrity behavior becomes highly non‑local. Disturbances in one region of the stack can affect timing, signal integrity, and reliability elsewhere. Power integrity in 3D-ICs is no longer a per‑die concern—it is a three‑dimensional, system‑scale problem.

Insight 2: Interconnect density has eliminated the margin for approximation

Advanced packaging dramatically increases interconnect density to support higher bandwidth and power delivery. Modern systems may incorporate tens of thousands of micro‑bumps, dense TSV arrays, and a rapidly growing number of VDD and VSS connections.

This density exposes new PI failure modes:

• Localized IR drop driven by fine‑pitch vertical structures
• Simultaneous switching noise (SSN) amplified by shared inductive paths
• Impedance resonances spanning dies, interposers, and package planes
• Frequency‑dependent coupling that varies with workload behavior

In AI/ML systems, these effects are highly dynamic. Bursty compute patterns, accelerator wake‑up events, and fast current transients make worst‑case conditions difficult to predict using static or approximate models. With voltage margins continuing to shrink, PI accuracy becomes a gating factor for performance, yield, and time‑to‑market.

Insight 3: TSVs and interposers demand scalable, multi‑physics solutions

In advanced 2.5D and 3D-ICs, TSVs and interposers are no longer secondary structures. They are central to both power delivery and thermal transport, and their behavior must scale with rapidly increasing system complexity.

As TSV counts climb into the tens of thousands and interposers carry ever‑higher current densities, multiple challenges emerge simultaneously:

• Scalability of electrical extraction, where dense TSV arrays introduce strong mutual inductance, capacitive coupling, and substrate interactions
• Vertical current concentration, increasing localized IR drop and L·di/dt noise across shared TSV and micro‑bump networks
• Thermal gradients along vertical power paths, where self‑heating alters resistance and exacerbates voltage droop

These effects are tightly coupled. Electrical behavior drives temperature rise, and temperature in turn modifies electrical characteristics. As a result, power integrity in 3D-ICs is inherently electro‑thermal, not purely electrical.

This coupling becomes even more critical as the industry adopts advanced thermal strategies. Liquid cooling, direct‑to‑package cold plates, and micro‑fluidic interposers are increasingly used to manage AI‑driven power densities. While these techniques increase thermal headroom, they also introduce:

• Non‑uniform temperature distributions across dies and interposers
• Spatially varying electrical behavior within the power domain network (PDN)
• A stronger need for accurate, scalable modeling that reflects real operating conditions

In this environment, TSV and interposer analysis must scale not only in size, but also must become more physically realistic. Simplified or geometry‑limited approaches struggle to deliver actionable PI confidence at the system scale.

Insight 4: The package has become a dominant power integrity element

As more power delivery shifts off‑die, the package increasingly dominates PDN behavior, especially across the mid‑to‑high frequency ranges that matter most for AI workloads. Key package‑level challenges include:

• Plane resonances that interact with die‑level decoupling strategies
• Via and trace inductance contributing to impedance peaks
• Return‑path discontinuities created by complex routing and stacking
• Broadband electromagnetic behavior, spanning MHz to multiple GHz

These effects are inherently frequency‑dependent and difficult to capture using DC or low‑frequency approximations. Yet they can amplify noise across multiple dies simultaneously, undermining system stability. Understanding package behavior in the context of the full 3D system is now essential for robust PI signoff.

Insight 5: Fragmented PI flows cannot keep pace with 3D systems

Despite the system‑level nature of the problem, PI analysis is often split across separate die‑, interposer‑, and package‑level tools and teams. This fragmentation introduces risk:

• Inconsistent assumptions about connectivity and power domains
• Manual data stitching that is difficult to maintain and error‑prone
• Late discovery of system‑level issues, when fixes are most costly

As 3D-IC complexity continues to scale, successful teams are those that move beyond siloed analysis toward unified, system‑centric power integrity workflows.

Enabling system‑level power integrity

Meeting the power‑integrity challenges of AI‑driven 3D-ICs requires a coordinated solution that spans modeling accuracy, scalability, and system integration. Siemens enables this through a complementary set of technologies:

• Calibre xACT3D for scalable, physics‑based RLCK extraction of TSVs, micro‑bumps, RDLs, and interposers
• Innovator3D IC Advanced Package Solver for broadband electromagnetic extraction of package PDNs, capturing frequency‑dependent impedance and resonance behavior
• mPower and HyperLynx SI/PI to enable realistic, workload‑aware system‑level PI simulation
• Innovator3D IC Integrator to assemble dies, interposers, and packages into a single, electrically consistent system model

Together, these capabilities support earlier risk identification, faster iteration, and confident power‑integrity signoff for the most advanced 3D-IC designs.

Fig. 2: Power integrity flow with Innovator3D IC Integrator.

What this means for semiconductor leaders

AI and heterogeneous integration are redefining what it means to deliver power reliably. Success now requires a shift:

• From local analysis to system‑level visibility
• From approximate modeling to scalable, physics‑based extraction
• From fragmented verification to integrated PI signoff

By adopting a system‑level approach to power integrity, semiconductor teams can unlock the full performance potential of 3D-ICs while reducing risk, improving yield, and accelerating time‑to‑market in the age of AI.

To learn more, download the full paper and discover how system-level PI analysis can de-risk your next 2.5D or 3D-IC design.

Sudarshan Deo is a software R&D manager for 3D IC at Siemens Digital Industries Software. Deo has expertise in implementing and integrating complex 3D IC workflows, including physical design, DFT, multi-physics, thermal, stress, SI, PI, DC IR-drop analysis, and advanced AI frameworks, and he serves as a technical point of contact for divisions across Siemens Digital Industries Software. Deo holds an M.S. in Computer Science from California State University, Sacramento.