Engineering The Signal For GDDR6


DDR1 through DDR3 had their challenges, but speeds were below one gigabit and signal integrity (SI) challenges were more centered around static timing and running pseudo random binary sequence (PRBS) simulations. Now, with GDDR6, we are working on 16 to 20 gigabits per second (Gbps) signaling and even faster in the near future. As a result, engineering the signal for GDDR6 will require careful ... » read more

2.5D, 3D Power Integrity


Chris Ortiz, principal applications engineer at ANSYS, zeroes in on some common issues that are showing up in 2.5D and 3D packaging, which were not obvious in the initial implementations of these packaging technologies. This includes everything from how to build a power delivery network to minimize the coupling between chips to dealing with variability and power integrity and placement of diffe... » read more

The Week In Review: Design


M&A Synopsys acquired Silicon and Beyond, a provider of high-speed SerDes and ADC/DAC IP. The company was founded in 2012 as SilabTech and headquartered in Bangalore. Synopsys highlighted the team of R&D engineers with high-speed SerDes expertise that would be joining with the acquisition. Terms of the deal were not disclosed. ANSYS will acquire OPTIS, a provider of software for sci... » read more

In-Design Rail Analysis Is A Beautiful Thing


As a long time designer, ASIC flows amaze me and making them better is my goal. Although a very complex and intricate process, each part of the ASIC flow abstracts the complexity underneath it to ultimately create silicon that could end up in your smartwatch, your electric vehicle, or the latest cell phone – how amazing! Consumers concerns include product reliability and robustness, which bri... » read more

Addressing Power Integrity Challenges For SoCs


Power integrity has become a crucial part of the system-on-a-chip (SoC) design flow because power-related issues can affect chip timing and even lead to complete device failure. Specifically, excessive rail voltage drop (IR-drop) and ground bounce can create timing problems and electromigration effects that impact a chip's performance and reliability. Analyzing a chip's power also poses diff... » read more

Creating Reliable SoCs For Safe ADAS Applications


Every major automaker is in the process of bringing out autonomous vehicles with ADAS (advanced driver assistance systems). In addition to processors and embedded software, ADAS requires a variety of sensors – ultrasonic, camera, RADAR (radio detection and ranging), LIDAR (light detection and ranging), GPS and IR (infrared) – that are used to recognize signs, people, animals, other vehicles... » read more

Managing Voltage Drop At 10/7nm


Power integrity is becoming a bigger problem at 10/7nm because existing tools such as static analysis no longer are sufficient. Power integrity is a function of static and dynamic voltage drop in the power delivery network. And until recently, static analysis did an effective job in measuring the overall robustness of PDN connectivity. As such, it is a proxy for PDN strength. The problem is ... » read more

10nm And 7nm Routability – How Is Your CAD Flow Doing?


At DesignCon in January, I was a panelist at a panel session entitled “Power Integrity For 10nm/7nm SoCs - Overcoming Physical Design Challenges And TAT.” I was on the panel together with Arvind Vel, Sr. Director Applications Engineering, ANSYS, Inc. and Ruggero Castagnetti, Distinguished Engineer, Broadcom Limited. This topic is of course extremely broad, but it was interesting getting fee... » read more

Routing Signals At 7nm


[getperson id="11763" comment="Tobias Bjerregaard"], [getentity id="22908" e_name="Teklatech's"] CEO, discusses the challenges of designs at 7nm and beyond, including power integrity, how to reduce IR drop and timing issues, and how to improve the economics of scaling. SE: How much further can device scaling go? Bjerregaard: The way you should look at this is [getkc id="74" comment="Moore... » read more

The Week In Review: Design


Tools Cadence launched its Sigrity 2017 technology portfolio for PCB power and signal integrity signoff, adding a power topology viewer and editor, library management for power integrity models, and a PCI Express 4.0 compliance kit for checking signal integrity. Memory Spin Transfer Technologies delivered samples of fully functional ST-MRAM (spin transfer magneto-resistive random acces... » read more

← Older posts