tag: power integrity

Delivering On Power During HPC Test
By Anne Meixner - 09 Jul, 2024 - Comments: 0

The industry’s insatiable need for power in high-performance computing (HPC) is creating problems for test cells, which need to deliver very high currents at very consistent voltage levels through the power delivery network (PDN). In response, ATE, wafer probe, and contactor vendors are introducing some innovative approaches and test procedures that can ensure robust power delivery to ATE pro... » read more

Powering Next-Generation Insightful Design
By Sara Louie - 24 Jun, 2024 - Comments: 0

The Ansys team is gearing up for an exciting time at DAC this week, where we’ll be sharing a whole new way of visualizing physical phenomena in 3D-IC designs, powered by NVIDIA Omniverse, a platform for developing OpenUSD and RTX-enabled 3D applications and workflows. Please attend our Exhibitor Forum session so we can show you the valuable design insights you can gain by interactively viewin... » read more

What’s At Stake In System Design?
By Cadence - 03 Apr, 2024 - Comments: 0

When engineers refer to system analysis, they are referring to tool functions for improving an overall electronics design. What you will gain from this eBook: Power and Signal Integrity Insights into harmonic balancing and crosstalk analysis Learning about loop gain and transmission rates Examining the necessity of power-aware systems Electromagnetic Analysis Knowledge ... » read more

Sigrity X — Redefining Signal And Power Integrity
By Cadence - 14 Feb, 2024 - Comments: 0

This white paper highlights the features in Cadence Sigrity X signal and power integrity (SI/PI) solutions for system-level SI and PI analysis that enable designers to cut the number of design respins and meet short time-to-market windows with confidence. Click here to read more. » read more

Next-Gen Power Integrity Challenges
By Ed Sperling - 14 Dec, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss power integrity challenges and best practices in designs at 7nm and below, and in 2.5D and 3D-IC packages, with Chip Stratakos, partner, physical design at Microsoft; Mohit Jain, principal engineer at Qualcomm; Thomas Quan, director at TSMC; and Murat Becer, vice president at Ansys. What follows are excerpts of that conversatio... » read more

Power Integrity Analysis For High-Performance FPGAs
By John Wagnon - 12 Jan, 2023 - Comments: 0

Efinix high-performance Titanium field-programmable gate arrays (FPGAs) are custom-tailored for the computing demands of mainstream applications, targeting markets from intelligent edge devices to industrial automation to vision systems to edge servers and communications (figure 1). Efinix customers use the Titanium line of FPGAs to ensure their complex, high-performance designs minimize power ... » read more

Ensuring Signal And Power Integrity In Today’s High-Speed Designs
By Pavani Jella - 08 Dec, 2022 - Comments: 0

Leading-edge chip desiLeading-edge chip design was never easy, but it’s getting harder all the time. Rapid advances in communication systems are driving data rates higher. With the emergence of artificial intelligence (AI) applications and the increased need for data processing, high quality data transfer is increasingly critical. Faster data rates and more complex protocols are exacerbating ... » read more

Ensuring Data Integrity And Performance Of High-Speed Data Transmission
By Cadence - 05 Oct, 2022 - Comments: 0

In key electronics applications such as data centers, automotive, and 5G, the data speed and volume are increasing at an exponential rate. Data centers require data transmission (Figure 1) as high as 112Gbps, which can be achieved only using PAM4 signaling. The automotive industry is dealing with the challenges of transferring data between various electronic control units (ECUs) at a very high ... » read more

Minimizing EM/IR Impacts On IC Design Reliability And Performance
By Joel Mercier - 13 Sep, 2022 - Comments: 0

By Joel Mercier and Karen Chow As technologies and foundry process nodes continue to advance, it gets more difficult to design and verify integrated circuits (ICs). The challenges become even more apparent in 5nm and below nodes, and as the industry moves away from fin field-effect transistor (finFET) and into gate-all-around field-effect transistor (GAAFET) technologies. There are many prob... » read more

Overcoming The Growing Challenge Of Dynamic IR-Drop
By PV Srinivas - 24 Mar, 2022 - Comments: 0

IR-drop has always been somewhat of an issue in chip design; voltage decreases as current travels along any path with any resistance. Ohm’s Law is likely the first thing that every electrical engineer learns. But the challenges related to IR-drop (sometimes called voltage drop) have increased considerably in recent years, especially the dynamic IR-drop in the power/ground grid as circuits swi... » read more

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