Photoluminescence Inspection Is Changing How Manufacturers Protect Yield In SiC And GaN Devices

Electric vehicles, fast-charging infrastructure, renewable energy systems, and industrial power conversion are redefining what power semiconductors need to deliver: higher voltages, higher power densities, faster switching, and longer lifetimes. To meet these demands, manufacturers are increasingly turning to wide-bandgap materials like silicon carbide (SiC) and gallium nitride (GaN).

SiC has become the material of choice for high-voltage applications such as traction inverters, onboard chargers, and motor drives, while GaN is widely adopted in fast-charging and high-frequency power devices. As these end products scale in volume and performance, the pressure on semiconductor manufacturing to deliver consistent yield and reliability continues to mount.

At the same time, manufacturers are undergoing critical transitions in wafer size. SiC production has moved from 150mm to 200mm wafers for high-volume manufacturing (HVM), with 300mm substrates for advanced packaging applications in early-stage development and limited demonstration. GaN, which historically has been manufactured on 200mm wafers, is also expanding into 300mm GaN-on-silicon. These transitions are essential for cost reduction, but they also introduce significant wafer handling, inspection, metrology, and yield challenges.

What conventional inspection misses

A defining characteristic of many SiC power devices is that they conduct vertically, from the front side of the wafer to the backside. This architecture fundamentally changes how defects impact performance and reliability.

In vertically conducting devices, crystalline defects that originate in the substrate or propagate through the epitaxial layers can directly create leakage paths, increase resistance, or cause catastrophic device failure. Some of these defects may be electrically benign at low stress levels, only to become yield-limiting once devices are operated at high voltage in the field.

This introduces a critical manufacturing challenge: not all defects are equal, and not all defects that matter are visible with traditional inspection techniques.

Traditional surface-based optical inspection is effective for detecting particles and some surface features, but it struggles to detect subsurface or crystalline defects that directly impact electrical behavior in wide-bandgap materials. As wafer sizes grow, these limitations become more pronounced.

Compounding the problem, many inspection systems rely on spinning-wafer architectures, which can introduce center-to-edge sensitivity variation, particularly as wafer sizes scale to 200mm and 300mm. This loss of uniform sensitivity becomes increasingly problematic at 200mm and even more so at 300mm, exactly where manufacturers can least afford blind spots.

For manufacturers scaling expensive SiC wafers, detecting defects is no longer enough. Understanding which defects are likely to impact yield and reliability is what matters most.

Photoluminescence (PL) inspection addresses this gap by enabling high-sensitivity, full-wafer detection of defect-related variations that are otherwise difficult to capture with conventional inspection approaches. When crystalline defects are present, they alter how the material emits light under excitation. In this way, manufacturers can use PL to reveal defect-related signatures and regions associated with performance variation, insights that are not visible with purely surface-based inspection techniques.

Fig. 1: Examples of defects identified by photoluminescence technology.

This capability is especially valuable for wide-bandgap materials where crystalline quality is tightly linked to electrical performance. PL inspection provides a powerful way to detect subsurface defects early in the process before device fabrication adds cost and complexity. High-sensitivity PL systems equipped with advanced optical designs and multi-channel detection provide the sensitivity needed to detect these subtle defect signatures across the full wafer.

As wafer sizes increase, inspection architectures must scale with them. XY stage inspection platforms, which scan the wafer without spinning it, maintain consistent sensitivity from the center to the edge of the wafer. This approach avoids the sensitivity roll-off inherent in spinning systems and provides a scalable and uniform inspection approach for larger wafers.

Equally important, modern PL inspection tools are designed with wafer-size flexibility in mind, enabling manufacturers to support current production needs while preparing for future substrate transitions without retooling their inspection strategy. While these advancements improve inspection capability, they do not fully address the need to connect defect data across the manufacturing flow.

Advanced manufacturers increasingly recognize that inspection tools cannot operate in isolation. Real value comes from integrating inspection, characterization, and data analysis into a coherent yield-learning strategy. This requires consistent, scalable correlation across optical, electrical, and process domains.

One example is sub-defect or root-cause defect mapping, where bare substrates are inspected first to establish an initial defect baseline. The same wafers are then re-inspected after epitaxial growth to identify which substrate defects propagate into the epi layers. This comparison enables manufacturers to distinguish between latent defects and defects directly threatening yield.

While traditional PL inspection can effectively detect and classify crystalline defects, it cannot determine which of these are electrically active and contribute to device failure. In contrast, non-contact electrical metrology based on corona-charged surface voltage mapping directly identifies and images electrically active defects linked to leakage currents and breakdown behavior in finished devices.

Combining PL and electrical defect imaging enables the correlation of specific epitaxial defect types with their wafer-scale spatial distribution and electrical activity, while also tracking substrate defects that persist through epitaxial growth. This provides a comprehensive view of defect impact on device performance, yield, and reliability.

By connecting defect location, type, and electrical activity, manufacturers can move beyond defect detection and begin assessing the true impact of individual defects on device performance and yield.

True defect intelligence

Beyond technical complexity, the economics of compound semiconductor manufacturing further amplify these challenges.

The economic stakes of compound semiconductor devices are high. A 200mm silicon wafer may cost a few hundred dollars, but a 200mm SiC wafer can cost an order of magnitude more than silicon wafers. Costs rise even further at larger diameters. Scrapping wafers late in the process or shipping marginal devices that fail in the field is no longer acceptable.

By detecting critical defects earlier, correlating optical and electrical data, and accelerating root-cause analysis, integrated inspection strategies help manufacturers protect yield, improve process learning, and confidently scale production.

As end-market products continue to push performance boundaries, power semiconductor manufacturing must evolve in parallel. Vertically conducting wide-bandgap devices demand inspection solutions that go beyond surface detection and deliver true defect intelligence.

As a result, inspection strategies must evolve from isolated detection steps to integrated, data-driven approaches that connect defect detection with process insight. Photoluminescence inspection, when combined with scalable system architectures, electrical characterization, and integrated data analysis, provides manufacturers with the tools needed to meet these challenges.

Increasingly, the value of these capabilities lies not in any single technique, but in how they are brought together within a unified inspection and analysis ecosystem, an approach that depends on tightly integrated system architectures, multi-modal data correlation, and scalable workflows to convert defect data into actionable process insight. For next-generation power semiconductors, this integrated approach is not just beneficial, it is becoming essential.