The chip industry has gone from two routing platforms to five. That’s a lot.
For decades, electronics offered two levels of routing structure to manage signals that originate or terminate in an integrated circuit. Recently, that number has risen to five, and while it adds far more flexibility for structuring electronic equipment, it also brings greater complexity and ratchets up the number of design decisions needed to complete a project.
This transition has been evolutionary, not revolutionary. Each step happens one at a time as developers identify solutions and as each barrier arises. As with the proverbial boiling frog, we acclimate to each change such that the magnitude of the accumulated change may not be evident until we step back and compare where we were to where we are now.
The starting point
For purposes of this article, a routing “structure” or “platform” is defined as a locus of interconnect. Historically, the two such platforms are metal routing on the IC itself and the PCB. Each provides multiple layers of routing to maximize connectivity while balancing against the cost of adding layers. The terms “layer” and “level” must be applied carefully here, because the IC and PCB are two levels of interconnect, each of which can contain multiple routing layers.
Fig. 1: Two levels of interconnect. The first level is the interconnect on the die itself. The die is mounted on a PCB, which is the second level of interconnect. Each level can have multiple routing layers. Source: Bryon Moyer/Semiconductor Engineering
Until recently, the two levels have been distinct enough so that they could be addressed separately. Chip designers build the on-chip routing level, whereas PCB designers build the routing that connects the IC to other components on the board.
On these and all other levels, there’s a tradeoff between line pitch and number of layers. Adding layers increases the cost, but it may take pressure off the routing on any given layer. “While adding layers can ease routing density, it also increases patterning complexity and sensitivity to lateral etch effects,” said Daniel Soden, product manager for lithography materials at Brewer Science. “Wider pitch and more tolerant structural designs can help manage those tradeoffs.”
Two is too few
Three developments challenged this simple arrangement. Performance has risen to a point where the lines on which a signal travels matter more than ever. Long lines hurt performance, and the traditional configuration provides two interconnect scales — the on-chip scale, where line dimensions are measured in nanometers, and the PCB scale, where dimensions are on the order of microns and millimeters. These differ by up to six orders of magnitude. There has been no practical in-between.
The second development has been the rise in chip power. When power ascends to the thousand-watt range, the heat produced becomes more challenging to dissipate. The primary thermal path in older packaging has been through the leadframe and into the metal lines on the PCB. More challenging cases include a heat sink atop the chip package. That has increasingly proven inadequate.
The third development comes from the relentless move to further integrate chips into smaller spaces. That can mean more circuits per chip and, in the older simple case, more chips per PCB. This exacerbates the power issue such that power density — that is, power per area or volume — can rise faster than power. High power density compounds the thermal challenges since more heat must escape a smaller volume.
Help from the package
As chips grew, the number of necessary I/Os grew, and leadframes proved inadequate. Instead, flip-chip packaging inverted the die, employed bumps instead of leadframes, and, critically, attached to a package substrate rather than a leadframe.
A substrate is fundamentally a small PCB built out of organic material with dimensions finer than is possible on a PCB. The simplest has one layer, but there can be multiple layers, which makes this a new level of interconnect.
Fig. 2: Package substrates form a new routing platform between the die and the PCB. Source: Bryon Moyer/Semiconductor Engineering
The substrate is now part of the package design. Traditionally, package design and chip design have been separate, with each tossing critical information over the wall to the other.
Substrate lines can be more aggressively drawn than PCB lines. That can be good and bad. Shorter lines improve signal quality, but narrower and closer ones don’t. Thermal arrangements are similar to the leadframe version, but more I/Os are available to wick heat down onto the PCB through the substrate. And heat sinks (or more advanced cooling) are still an option when necessary.
It’s possible to mount multiple chips on a substrate as long as the area and line pitch allow it.
Stack ‘em up
The next obvious way to pack more into less space is to stack multiple chips atop each other in a 3D configuration. The interconnect enabling this is the set of through-silicon vias (TSVs) that allow signals to travel vertically between the chips. TSVs provide less flexibility than the other interconnect levels because each carries a single signal.
Multiple TSVs exist, but it’s not like they’re routing resources that some routing algorithm can take advantage of. Their locations are flexible, but the signals they carry are fixed. That said, selection of which signals go on the TSVs is part of the overall partitioning process as one decomposes a big problem into pieces. For some chips, such as HBM, those signals may be obvious. But in the general case, they may not be.
Fig. 3: Stacked chips. The through-silicon vias (TSVs) serve as another level of interconnect, although they’re a less flexible resource than the other levels. Source: Bryon Moyer/Semiconductor Engineering
Chip stacks raise the thermal stakes tremendously, since those chips in the middle of the stack lack an escape path for their heat. With a single die in a package, the heat can leave through any of the six facets of the die, and the top and bottom, in particular. In a stack such as this, however, the chips above and below are generating their own heat — heat that wants to travel into neighboring chips even as they try to send their heat up or down.
Dissipating the heat from such stacks is an ongoing challenge. Materials surrounding the stack may change to dissipate more heat out the sides of the stack rather than relying so much on the top and bottom.
How tall and robust stacks will be depends on the bonding technique. Traditional micro-bump interconnect predominates today, but hybrid bonding is making strides. “Hybrid bonding is a higher performance solution — at a higher cost,” observed Vikas Gupta, director of engineering and technical promotion at ASE Group.
And interposers make five
Nearly concurrent with the development of die stacks was 2.5D integration, which involves interposers that act as an intermediate “PCB” with much finer line pitch than is available in a PCB or a substrate. Multiple chips or chiplets can be mounted atop it instead of the PCB. The main difference is that only packaged units go onto a PCB, while bare chips are mounted on an interposer or substrate. Line spacing can be more aggressive on an interposer than on a substrate.
Interposers may be organic, as a PCB is, or they can be made of silicon. The latter allows finer dimensions, whereas the former is less expensive. They can have multiple routing layers, numbering around four today, but expected to grow to around eight or nine. Without an interposer, a single die or stack sends all I/Os out of the package to the PCB. With an interposer, many of those signals will go no further than the interposer.
Interposer-only signals result from one of two approaches. The obvious one is that chips that might have co-resided on a PCB can now co-reside inside the package, and their mutual connections never have to see the light of day.
The less obvious one means that what was once a single monolithic die can be split into multiple chiplets. “You’re taking apart a very large SoC, and you’re trying to partition it into smaller chips and chiplets,” said Shawn Nikoukary, senior director for SoC engineering at Synopsys. “And in doing so, you are trying to improve your PPA — the power, performance, and area.”
The internal signals that might have remained on a monolithic implementation now leave one chiplet and re-enter another. Line spacing on the interposer is less aggressive than that on the chip itself, but silicon interposers can still provide narrow lines and spaces — although they may be highly resistive.
Fig. 4: Five levels of interconnect, shown in order of extent. The first level is on-die routing. The second consists of the TSVs that enable die stacking. The third is an interposer, and the fourth is the die substrate. The fifth and final level is the PCB. Beyond that, further interconnects typically employ wires or fiber. Source: Bryon Moyer/Semiconductor Engineering
A major challenge as interposers grow is mechanical warpage driven by the many layers having different thermal expansion rates. “Metal thickness is around 1.5 to 2.0µm,” explained Pax Wang, director for advanced packages at UMC. “The total dielectric thickness is around 15 to 20µm on top of the silicon substrate. Wafer warpage will be dramatically increased by traditional silicon processes.”
Cost is also a challenge, with silicon interposers (which have the tightest line pitch) costing more than organic ones. Forgoing an interposer and using the substrate instead could help, assuming the substrate design rules permit it. “Using the substrate to replace the interposer layer will be a more cost-effective solution,” said Wang. “The pitch of the substrate is around 25 to 50µm. By comparison, for the organic interposer, the pitch is around 2 to 5µm, which makes the interposer architecture still highly relevant for high-performance computing applications.”
Silos crumble
The process of designing and verifying a five-level system has become far more complex than in previous decades, which had chip and package designers on opposite sides of a wall. PCB design is still separate, but four of the five levels are inside the package, and the entire package’s contents must be designed and verified together.
Even considerations as trivial as whether to have a lid on the package must be evaluated, especially when planning cooling. “Some customers want to have a lid on the package,” said Mike Kelly, vice president, chiplets/FCBGA integration at Amkor. “It’s great for mechanical robustness, especially for test, for handling in the assembly shops. Other customers have already had to depart from the lid and put the cooling solution directly down on the backside of the die.”
It’s at the early architectural stages that these interconnect levels provide maximal flexibility. If the design process includes the splitting up of an erstwhile monolithic design, the easiest approach may be to deal at the block level to see where to split things. But the routing resources in the various levels have a strong impact on routability. Some partitions will route better than others.
Much more to verify
Verification starts at this early phase and covers far more than routability. “It will start with structural material analysis, such as the RDL stack-up requirements, material stack-up and their properties,” said Lihong Cao, senior director at ASE Group. “Then your goal is to do the pre-analysis, including the floor plan, warpage, and electrical simulations.”
Satya Karimajji, senior engineer for SoC engineering at Synopsys, agreed. “You can focus at the architecture level: What are the power numbers we’re going to see? What’s the heat flux? And what cooling methodology can we anticipate? Evaluating the thermal integrity at the chip level will help too. We can improve the thermal design by optimizing materials used, how the blocks are placed, how they are stacked, etc.”
But it must be more than just the chip, including several levels of mechanical container. “Another level would be the enclosure, where the package and PCBs lie and air flows — or liquid cooling, or whatever thermal management approach we’re using,” added Nikoukary.
The process necessitates multi-physics tools since these additional considerations lie far outside the bounds of functional verification. These are all considerations that used to be handled individually. They are now part of the overall chip design process.
Whether coming as a result of higher integration or monolithic disaggregation, the individual chips will have their respective design teams as before. It’s just that their specifications can’t be ready until the higher-level architecture has been determined. Design teams can work on their individual chips or chiplets in isolation, but an integrator must take the individual designs and ensure that they work together properly.
The integration team’s tasks include verifying not only functionality, but also signal integrity, power integrity, physical robustness against effects such as warping, and overall thermal performance. This verification was done earlier with estimates. Now comes final verification to confirm the design outcomes.
Power rushes in
Additional levels of interconnect also provide an opportunity for more nuanced power delivery and signal quality schemes. Whereas voltage regulation was once relegated to the system level, with wires delivering the power to a board, voltage regulation is now moving as close to the die as possible, and that includes placing voltage regulators inside the package. They may be mounted on the substrate or the interposer.
Signal integrity is also boosted through the use of decoupling caps (decaps) to buffer against voltage excursions. With older single chips, those tend to be placed near the regulator and near the chip on the PCB (with the possibility of small on-die metal-oxide-metal — MOM — or metal-insulator-metal — MIM — capacitors). With advanced packages, those decaps can move under the package, onto the substrate, or onto the interposer. New technologies are also making them available within the core of a substrate or interposer.
In other words, each of these interconnect levels — die, stack, interposer, substrate, PCB — provides an opportunity for moving power and decaps closer to the die. One wouldn’t typically find them at all five levels today, but the possibility remains for future designs that push the limits of performance even further.
The result of years of development
Rather than a revolutionary shift, this is more of an opportunity to step back and see the results of many years of incremental change. Each of those changes provided challenges of its own. Taken together, however, there’s a big difference between how we handle simple, old-style chips and new complex ones.
The five-level construct may or may not inform daily decisions as we develop new chips. At the very least, it gives us some perspective on how much both flexibility and complexity have grown. Such thinking can be beneficial at the architectural level, where all the levels are potentially in play.
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