Searching For Power Bugs


How much power is your design meant to consume while performing a particular function? For many designs, getting this right may separate success from failure, but knowing that right number is not as easy as it sounds. Significant gaps remain between what power analysis may predict and what silicon consumes. As fast as known gaps are closed, new challenges and demands are being placed on the ... » read more

Power And Performance Optimization At 7/5/3nm


Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at Synopsys; Bryan Bowyer, director of engineering at Mentor, a Siemens Business; Kiran Burli, senior director of marketing for Arm's Physical Design Group; Kam Kittrell, senior product management group d... » read more

Monitoring Heat On AI Chips


Stephen Crosher, CEO of Moortec, talks about monitoring temperature differences on-chip in AI chips and how to make the most of the power that can be delivered to a device and why accuracy is so critical. » read more

On-Chip Monitoring Of FinFETs


Stephen Crosher, CEO of Moortec, sat down with Semiconductor Engineering to discuss on-chip monitoring and its impact on power, security and reliability, including predictive maintenance. What follows are excerpts of that conversation. SE: What new problems are you seeing in design? Crosher: There are challenges emerging for companies working on advanced nodes, including scaling and trans... » read more

Extending The IC Roadmap


An Steegen, executive vice president of semiconductor technology and systems at Imec, sat down with Semiconductor Engineering to discuss IC scaling and chip packaging. Imec is working on next-generation transistors, but it is also developing several new technologies for IC packaging, such as a proprietary silicon bridge, a cooling technology and packaging modules. What follows are excerpts of t... » read more