Paving The Way To Chiplets


The packaging industry is putting pieces in place to broaden the adoption of chiplets beyond just a few chip vendors, setting the stage for next-generation 3D chip designs and packages. New chiplet standards, and a cost analysis tool for determining the feasibility of a given chiplet-based design, are two new and important pieces. Along with other efforts, the goal is to propel the chiplet m... » read more

A Broad Look Inside Advanced Packaging


Choon Lee, chief technology officer of JCET, sat down with Semiconductor Engineering to talk about the semiconductor market, Moore’s Law, chiplets, fan-out packaging, and manufacturing issues. What follows are excerpts of that discussion. SE: Where are we in the semiconductor cycle right now? Lee: If you look at 2020, it was around 10% growth in the overall semiconductor industry. ... » read more

Scaling Bump Pitches In Advanced Packaging


Interconnects for advanced packaging are at a crossroads as an assortment of new package types are pushing further into the mainstream, with some vendors opting to extend the traditional bump approaches while others roll out new ones to replace them. The goal in all cases is to ensure signal integrity between components in IC packages as the volume of data being processed increases. But as d... » read more