A Broad Look Inside Advanced Packaging

JCET’s CTO talks about the slowdown in Moore’s Law and the growing interest in new packaging approaches and chiplets.


Choon Lee, chief technology officer of JCET, sat down with Semiconductor Engineering to talk about the semiconductor market, Moore’s Law, chiplets, fan-out packaging, and manufacturing issues. What follows are excerpts of that discussion.

SE: Where are we in the semiconductor cycle right now?

Lee: If you look at 2020, it was around 10% growth in the overall semiconductor industry. Then, in 2021, it is expected to be about 24% growth. This can be attributed to the Covid situation. Everyone is buying all types of systems to connect with each other. But if you look at 2022, it looks like single-digit kind of numbers. Still, in terms of the semiconductor compound annual growth rate, or CAGR, it looks solid. It’s just that 2021 is really exceptional. I’m not taking in account the other parameters like inflation or other factors. If you look at the pure semiconductor market, it looks okay.

SE: What are some of the big drivers in the chip market?

Lee: Automotive is one of the driving forces. Even though there are chip shortages here, automotive is still growing. Then, electric vehicles, autonomous driving and so on are fueling the growth. And for some time, the automotive industry has been focusing on safety. You have safety-related features in cars like sensors or even ADAS. That’s a big driver in automotive. The electronic content in many cars is around $600 per car. It’s going up from there. Electronic content in cars will increase. Then, for 5G-related applications, you have car-to-car or vehicle-to-vehicle (V2V) communications. That’s driving the high-end infotainment market. This technology is still in the early stages. Every carmaker is looking at that.

SE: What else is driving the semiconductor market, and what impact does that have on packaging?

Lee: Another driver is AI. AI involves high-performance computing (HPC). We are seeing a lot of demand for flip-chip BGA, which is linked to AI or HPC applications. That also includes 2.5D, 3D, or high-density fan-out. The cloud is a big market for AI. The adoption rate here in data centers continues to increase. Data centers are also enhancing their efficiency and reducing their operational costs. The amount of data is increasing at a tremendous rate.

SE: What about 5G?

Lee: In the communication sector, there is 5G. But 5G is not in the mature stages yet. It’s still in the early stages. Because of the Covid situation, some countries delayed or slowed their infrastructure buildouts of 5G. Next year, many will focus on bringing up the infrastructure in 5G. Every phone maker is serious about incorporating 5G content in their smartphones. For the OSAT market, 5G is a big driver. We have been expanding our capacity and putting the infrastructure in place for 5G demand, especially for system-in-package (SiP). In 5G, you also have AiP, or antenna-in-package, as a new feature in a package.

SE: How do you view Moore’s Law?

Lee: Moore’s Law, by definition, involves doubling the chip density every two years. But that isn’t happening anymore. It’s slowing down. But we can look at this from a different aspect. We’ve heard about a 40% performance increase at each node. But in terms of its original definition, Moore’s Law isn’t really catching up. It’s not really dead. It is slowing down.

SE: At the same time, the older technologies are booming. There is huge demand for chips at mature nodes in older 200mm fabs, right?

Lee: It’s amazing. Even in the OSATs, the 8-inch wafer-level demand is huge. In some cases, it’s bigger than 12-inch. It’s an inflection of the industrial transformation. As we discussed, automotive is a big driver here. Then, we have industrial IoT. Demand for analog is huge, even in automotive. Power is becoming more critical when it comes to technologies like electric vehicles.

SE: IC packaging isn’t new, but years ago it was largely in the background. A given IC package simply encapsulated and protected a chip. Recently, though, packaging has become more important across all industries. What changed?

Lee: The smartphone market drove some of the first changes. In a sense, there are more functions embedded in smartphones. If you look at the 3G, 4G, and 5G evolution, the smartphone incorporates more dies in the same motherboard area. That drove everything toward a SiP-type of format. The x, y, and z form factor became a critical parameter for the smartphone, along with evolution from 3G to 4G and 4G to 5G. Another driver is the high-performance computing area. Then, with (TSMC’s) InFO, RDL technology became a baseline for a packaging format in advanced packaging.

SE: Chiplets are a hot topic because they allow you to choose from a menu of modular dies. What are you seeing?

Lee: Everyone is talking about chiplets. Even before chiplets, people were thinking, ‘I would like to have a different and functional SoC in a package-like architecture instead of a traditional monolithic SoC.’ That’s another change that impacts packaging. In a sense, this kind of advanced package, or advanced product, requires high-density interconnects. So in that context, packaging itself is no longer just a single die in a package with encapsulation. In more advanced packaging, you have to think about the layout, the interactions with the chip and the package, and how to route these layers. These are becoming some of the fundamental parameters to think about when device makers design their own chips. Chiplets are already in the market. This concept is coming from the IDMs or the device makers. They look at the package as part of their product performance and product launch.

SE: How do you see this playing out?

Lee: From a system point of view, a chiplet is a multi-die architecture. From an OSAT’s perspective, the question is how do you really optimize the layout to get the optimal performance or maximum performance in the package. In some respects, the definition of a chiplet is being driven by the device makers. The device guys envision the idea of breaking up an SoC. Analog would be at one node. Then, you might have 16/14nm/7nm IP. The argument is you get better wafer yield and save money. They are thinking about how to disaggregate the discrete functions out of a monolithic SoC design. Right now, AMD is very active in chiplets. They are working with TSMC on SoIC. They have already implemented this architecture and made improvements to the performance. AMD has fully utilized this advanced packaging concept.

SE: In 2015, JCET acquired STATS ChipPAC. JCET offers a broad portfolio of packaging and assembly services with worldwide operations. What comes next?

Lee: We have an expansion plan. JCET management has approved a sizable CapEx for the years to come, and we have prepared the space in order to expand the capacity. As a leading figure in the OSAT market, we rely on the continuous investment in technology and manufacturing capacity.

SE: We’ve seen several foundries expand their packaging efforts, such as Intel, TSMC, and Samsung. Any thoughts here?

Lee: In many ways, the foundries focus more on advanced packaging formats, something like SoIC from TSMC. That’s a foundry front-end process. We want to focus on our own capabilities. Wafer-level fan-out packaging is an example. We are working on 2μm x 2μm with high performance and good yields.

SE: Let’s talk about the various packaging types. What about wire bond? It’s still a big business, right?

Lee: In terms of the number of units in semiconductors, wire bonding takes up like 80%. Take a look at the evolution at wire bonding technology. In our factory, we’re handling something like 2,500 wires in a package. One factor in wire bonding is cost. The other one is reliability. Leadframe-based or LGA packages are inexpensive. It’s a two-layer organic substrate. But it’s a huge number of units. We have spent a lot of money to expand the capacity here.

SE: Fan-out packaging is gaining steam, and JCET is no stranger to this approach. The company has a long history with embedded wafer-level ball grid array (eWLB), right?

Lee: JCET’s Singapore operation was one of the early entrants in eWLB. They started eWLB from the very beginning with a license from Infineon. But fan-out is a fragmented market segment. We are trying to go into different market segments here. It’s a good fit for the low-volume, high-mix market, but it’s still valuable in terms of performance. It has some advantages with its x, y, and z form factors. Right now, we see the growth in eWLB. That’s the low-end of fan-out.

SE: JCET recently entered the high-density fan-out market with a technology called XDFOI. What’s that about?

Lee: JCET recently announced plans with XDFOI. This is basically a chip-last, RDL-first, high-density fan-out technology. We are developing RDLs with 2μm line and space. In contrast, eWLB is 10μm/15μm line and space. We are moving into the high-density fan-out market to provide new options for customers. Many see a value proposition using fan-out without the silicon interposer. So we plan to have a high-end fan-out offering from JCET.

SE: Several companies offer high-density fan-out, which can support high-bandwidth memory (HBM) memory and other complex devices. What’s the interest level for your technology?

Lee: Definitely, we have customers for our high-density fan-out with different memory configurations.

SE: Where are the line/space geometries heading in the high-density space?

Lee: Right now, 4μm x 4μm is used in high-volume manufacturing (HVM), and 2μm by 2μm is moving to HVM. In regard to the resolutions, steppers can handle 1μm x 1μm. But the challenge is to achieve the yields. Without achieving the yields, there is no value at all. Our focus is to achieve high yield. High yields translate well above 99% with a four-layer RDL and a 2μm line and space.

SE: Are you using traditional steppers or direct-write for your lithography flow?

Lee: We use the conventional stepper. We are using an advanced system. We can do 2μm x 2μm.

SE: The big challenge with fan-out is die shift and warpage, right?

Lee: Die shift isn’t really the major issue in 2μm x 2μm. When you go down to these fine lines and spaces, particles are the killer in the process. Particles are the biggest challenge.

SE: And, of course, that means you need more inspection tools?

Lee: Exactly. In normal RDLs like 10μm line and space, the undercut is 1μm. If you have 2μm line and space, the undercut is a big challenge. It’s a totally different challenge when you compare 10μm x 10μm versus 2μm x 2μm. So you need to be very cautious about fine tuning the process.

SE: What is your view on panel-level fan-out?

Lee: Four or five years ago, I was very pessimistic. The issue is that there are no standards in terms of panel formats. At the time, there were equipment issues. There was a lack of maturity there. What’s the driving force today? The motivation of panel-level processing was cost compared wafer level. I’m not talking about the market itself, or which customers will adopt it. From the cost standpoint, a 12-inch line is already depreciated. If you want to start a panel line, you have to think about depreciation. That’s one issue. Then, whenever you have a new device, you need to undergo a full qualification process on panel. It’s a different qualification process from a wafer-level one. In one conference, I made the comparison between wafer-level versus panel-level. Take a codec-like chip at 7μm x 7μm, for example. Let’s say smartphone sales are roughly 1.4 billion. You need 1.4 billion units of this package for each phone as one example. Then, you might have a facility with 20,000 panels per month. Even a 10,000 square meter panel can handle 1.4 billion units.

SE: Any thoughts on hybrid bonding?

Lee: We have hybrid bonding on the roadmap. This has something to do with the bump pitch. Sony has been using hybrid bonding. Sony has been doing this a long time for CMOS image sensors. Now, everyone is working on hybrid bonding. It enables high-density die-to-die bonding. It’s basically copper-to-copper bonding. In hybrid bonding, you are not extending copper bumps, which consists of a tin-silver cap on copper. It’s just copper-to-copper. It’s a different interconnection process of wafer-to-wafer bonding.

SE: In today’s advanced packages, the chips are stacked and bonded using copper microbumps. The most advanced microbumps involve a 40μm pitch, which equates to 20μm to 25μm bump sizes with 15μm spacing between the adjacent bumps on the die. The industry is working on finer pitches beyond 40μm, enabling more I/Os. What’s happening here?

Lee: Now, 40μm is the common bump pitch for HVM. For 10μm, we are working on that. We are trying to build up our engineering data here. If customers want to go down to 10μm pitches for their own devices that involves die-to-die bonding, we will be capable of handling this. But when it comes to less than 1μm-like pitch, this is where it gets challenging. This is a foundry-like process. Generally, the capabilities for OSATs is down to 10μm, maybe past that pitch.

SE: Are you looking at thermocompression bonding here?

Lee: No. We actually are employing laser-assisted bonding (LAB) instead. Laser-assisted bonding shines a laser beam to the chips, where the bump tips are Sn or SnAg. LAB is used to connect them to the substrate. This gives a higher UPH (units per hour) and more robust interconnection than thermocompression. It provides much less residual stress than MR (mass reflow).

SE: Finally, what keeps you awake at night or worries you in the market?

Lee: In some cases, packaging technologies often overlapped with the foundries in terms of capabilities, making the business situation more dynamic in the OSAT environment in terms of CapEx investment and ROI, as well as having a dedicated manufacturing infrastructure with automation.

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