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System-In-Package Thrives In The Shadows

Multi-chip approach cuts across all package types, dominates smart phone and wearables markets.


IC packaging continues to play a big role in the development of new electronic products, particularly with system-in-package (SiP), a successful approach that continues to gain momentum — but mostly under the radar because it adds a competitive edge.

With a SiP, several chips and other components are integrated into a package, enabling it to function as an electronic system or sub-system. SiPs are especially useful where space is limited, such as in smart phones and wearables. Apple, for example, uses SiPs in a number of its products.

Originally conceived in the 1980s, SiPs come in different forms today. But the terminology can be confusing. Definitions vary from one company to the next, and a SiP can refer to both the actual combination of chips as well as the methodology for combining them into an electronic system or subsystem. A SiP can incorporate any combination of chips, passives, and sometimes MEMS, in either a commodity or advanced package.

To develop a SiP, customers choose from a number of technologies in a toolbox, such as the components, interconnects, materials, and packaging architectures. SiPs are manufactured at an OSAT and/or a contract manufacturer.

Fig. 1: An example of a SiP multi-chip module with CPU and memory, all mounted on the same substrate. Source: Wikipedia

SiPs are different than chiplets, but there is some overlap. Both approaches are solutions to the increasing difficulty and rising cost of developing SoCs at each new node. But with chiplets, a vendor or packaging house may have a menu of modular dies, or chiplets, and then mix-and-match the chiplets in an advanced package to create a system customized for a specific domain or application. As of today, only a few large players such as Intel, AMD and Marvell have developed proprietary chiplet-like designs, although foundries and OSATs are pushing to broaden that market.

In contrast, the components used in a SiP have been readily available for years. The SiP market already is a sizeable business, and it’s expected to grow from $14 billion in 2020 to more than $19 billion by 2026, according to Yole Développement.

“Almost every application these days has a SiP, such as smart phones, wearables, computers, telecom and automotive,” said Jan Vardaman, president of TechSearch International.

SiPs and other packages
Not all systems require SiPs, but they’re one approach to create complex and extremely fast systems more quickly without having to cram everything onto a single die. That could include everything from different accelerators and memories developed at the most advanced process nodes, to analog chips developed at established nodes.

Clearly, there is a need for faster chips to boost the compute power in systems. “There’s no question that being able to compute 10X faster than now will be commercially useful and competitively required,” said Aki Fujimura, chief executive of D2S.

Nonetheless, an IC package protects the various chips from being damaged and boosts the performance of the dies. So far, the industry has developed more than 1,000 different package types. Chip customers select a package type based on a given application.

In some cases, a SiP makes sense. SiPs can be traced back to the 1980s, when IBM developed multi-chip modules (MCMs) for its high-end computers. A form of SiP, MCMs incorporate dies in a module.

SiPs have evolved since then, integrating various components in either commodity or advanced packages. SiPs could be customized versions of these packages. In some circles, heterogeneous integration — assembling complex dies in an advanced package — falls under the broad category of SiPs.

“SiP encompasses a number of different enabling technologies that could support a broad range of market segments,” said Curtis Zwenger, vice president of advanced SiP product development at Amkor. “The markets we address for SiP include wireless, IoT, automotive, power management and computer networking.”

One way to segment the packaging market is by interconnect type, such as wirebond, flip-chip, wafer-level packaging (WLP) and through-silicon vias (TSVs). Interconnects are used to connect one die to another one.

Today, some 75% to 80% of packages are based on wire bonding, according to TechSearch. A wire bonder stitches one chip to another chip or substrate using tiny wires.

Wirebonders are used to make several package types, such as quad-flat no-lead (QFN). A QFN could incorporate a few simple devices or many of them. “We have seen QFNs that are 6mm x 6mm, and have dropped 15 components in there. We’ve seen some stacking there. It’s basically a system-in-a-package inside a small QFN,” said Sam Sadri, senior process engineer at QP Technologies.

Meanwhile, in flip-chip, a sea of tiny copper bumps is formed on top of a chip. The device is then flipped and mounted on a separate die or board. The bumps land on copper pads, forming an electrical connection.

Flip-chip is used to develop many packages, such as double-sided, molded ball grid array (DSMBGA) and others. Several OSATs have developed DSMBGA packages. Amkor is the latest one.

In DSMBGA, the components are situated on top and bottom of the substrate. This reduces the package size, and also shortens the signal path of the devices. The components can be tuned to enable a SiP.

DSMBGAs are found in smartphones and other products. Phones consist of a digital portion as well as an RF front-end module, which handles the transmit/receive functions.

“Double-sided packaging technology has increased the level of integration for RF front-end modules used in smartphones and other mobile devices,” Amkor’s Zwenger said. “Typically, it has power amps, switches, filters, and low noise amplifiers (LNAs). That’s the integration that we see for DSMBGA. It can be used for other types of integration, but this is a sweet spot.”

In phones, power amplifiers boost the power. LNAs amplify small signals, while filters block unwanted signals. RF switches route signals from one component to another.

Fig. 2: DSMBGA package. Source: Amkor

Fan-out WLP is another package option for SiPs. In one example of fan-out, a DRAM die is stacked on a logic chip.

2.5D/3D packages, meanwhile, are used in high-end systems. In 2.5D/3D, dies are stacked or placed side-by-side on top of an interposer, which incorporates TSVs.

Fig. 3: Different options for high-performance compute packaging, interposer-based 2.5D vs. Fan-Out Chip on Substrate (FOCoS). Source: ASE

SiPs for wearables
Wearables are a big driver for SiPs. Apple, FitBit/Google, Huawei, Samsung, Xiaomi and others compete in this market. Head-worn/hearable products are the largest segment in the wearables market, followed by wrist-worn products, body-worn, and smart clothing, according to Yole.

In total, the mobile/consumer SiP market was an $11.9 billion business. Of that, the wearables SiP market was a $184 million business in 2020, representing only 1.55% of the overall mobile/consumer SiP segment, according to Yole. By 2026, the wearables SiP market will reach $398 million, a 14% growth rate, according to Yole.

Each wearable market is different, but the requirements are similar. “The top needs for wearables are performance, light weight, comfort and better attachment. The results need to be more accurate. It requires more functions,” said Henry Lin, an associate marketing director at ASE, in a presentation at IMAPS’ recent Advanced System-in-Package (SiP) technology conference.

This is especially true for smart watches. Apple’s smart watch, dubbed the Watch 6, incorporates various features, including one that measures blood oxygen saturation. It also has an electrocardiogram (ECG) app.

The Watch Series 6 incorporates an application processor and other functions in Apple’s S6 SiP. The SiP incorporates Apple’s A13 processor based on TSMC’s 7nm process. The A13 is built around Arm’s dual-core 64-bit processor.

For the application processor, Apple uses a specific SiP. “Apple uses the InFO for the application processor. There are many other SiPs in the Apple Watch and other smartwatch products,” TechSearch’s Vardaman said. InFO is TSMC’s integrated fan-out packaging technology.

Other smartwatches use various packages. In all cases, OEMs face several challenges. “We expect all of these things on our wrists or in our ears to take up no space at all. This requires a focus on miniaturization that is intentional and integrated into the product development process,” said Pieris Berreitter, manager of hardware engineering at FitBit/Google, in a presentation at IMAPS’ SiP conference. (In 2019, Google acquired FitBit).

To enable products with smaller form factors, FitBit has taken a new design approach. At one time, FitBit developed the RF portions of a given wearable using discrete chips, which were then assembled on a board. “Before 2018, we were building discrete chip designs for our radios solving the RF challenges,” Berreitter said. “After a while, the radio designs started to look the same from product-to-product and generation-to-generation.”

That’s when FitBit began to look at SiPs. It looked at several criteria in developing a SiP, such as area, cost, manufacturing, reliability, reuse, test, and time to market.

SiPs have some tradeoffs. According to Berreitter, here are some of the advantages:

  • Combines several discrete components in a package, which saves board space;
  • Allows for reuse of analog/RF chips;
  • Saves time/money on RF test;
  • Good reliability.

According to the FitBit engineer, SiPs also have some disadvantages, including long fabrication times, and part costs that are sometimes more expensive than a discrete solution.

FitBit eventually moved from a discrete solution to a SiP for some portions of the product. In its older smartwatch, FitBit incorporated several discrete devices, such as a microcontroller, memory, GPS and various RF chips (Bluetooth, WiFi), on a 10mm x 20mm board.

Then, in the Versa 2 health/fitness smartwatch, FitBit integrated the RF components (Bluetooth, WiFi) in a SiP, enabling it to reduce the RF footprint in a smaller 10mm x 9mm board. The MCU and memory remain discrete products. The Versa 2 was introduced in 2019.

“We SiPed the simplest, lowest-risk systems that we knew we would use again. And we miniaturized those subsystems, which created the room for new features in the product,” Berreitter said. “We used the same radio architecture, but we were able to use some smaller components and tighter spacing rules for the radio.”

There are other benefits to SiPs. “We were able to go from a double-sided board to a single-sided board, thanks to a smaller area of the SiP. We could use this to our advantage in the product, using the backside of the circuit board as one side of a resonant cavity for the antenna. Now, we had a thinner product, and better antenna performance,” Berreitter said. “With Versa 2, the radio SiP allowed us to offer longer battery life, a microphone for voice assistance, and a better display.”

SiPs also have some implications for shielding in the design. Shielding is used to block interference between RF components. For this, OEMs use tiny enclosures called shield cans. These enclosures, which cover the RF chips, are soldered to the board.

In discrete solutions, shielding takes up board space. By combining chips in a SiP, OEMs can reduce the shielding content. Even so, shielding still involves several challenges. “When it comes to wearable devices, you have several RF wireless communication circuitries embedded into the SIP,” said Michael Liu, senior director of global technical marketing at JCET. “They are sensitive to any kind of interference, but they also have different frequency bands.”

FitBit, meanwhile, doesn’t integrate all components into a SiP, namely DRAM. A DRAM part may undergo several revisions over time. So it makes sense to use the latest revision as a discrete part, and not delay the SiP, in the design.

Then, in its latest Sense smartwatch, FitBit didn’t integrate its ECG feature into the SiP. Complex features like ECG take more time to develop, so it makes more sense to use a discrete solution, Berreitter said.

Hearables are another big market. Apple’s wireless earbuds, called AirPods, integrate Apple’s H1 chip and audio cores in a SiP. Those devices also include an accelerometer and gyroscope, according to Yole.

Going forward, OEMs are developing wearables with more functions, which presents some new challenges. “Thinner, denser and thermally efficient PCB/package designs are needed to meet various medical and consumer wearable requirements,” said Santosh Kumar, an analyst at Yole.

5G SiPs
SiPs also are found in 4G and 5G smartphones. The vast majority of today’s wireless networks revolve around the 4G LTE standard, which operates from the 450MHz to 3.7GHz frequency bands. 5G, meanwhile, is being deployed in two different frequency ranges — sub-6GHz and mmWave (28GHz and above). Compared to 4G, 5G promises to deliver mobile network speeds with a 10X lower latency, a 10X higher throughput, and a 3X spectrum efficiency improvement.

In wireless networks, operators deploy giant cell towers with massive MIMO antenna systems. Incorporating tiny antennas, a massive MIMO sends and receives signals to end-user phones by using beamforming techniques.

Today, 5G is a mixed picture. “The sub-6GHz version of 5G is being adopted quickly across the world,” said Raj Verma, associate vice president of technology development at UMC. “However, for mmWave, the rollout is taking longer than expected. Today, mmWave implementation requires a significant increase in land and building infrastructure investments. In addition, designs and systems for mmWave are also significantly more complex and taking a bit longer to develop.”

The problem is that mmWave has line-of-sight limitations, low penetration capabilities through walls, and a short range. So far, Apple and Samsung have adopted the lower end of mmWave frequency bands in their phones.

From a component standpoint, the sub-6GHz 5G smartphones resemble today’s 4G phones. The system consists of a digital portion and RF front-end modules. The main antenna is separate and runs alongside the phone.

5G mmWave phones are different. In Apple’s iPhone 12, for example, the system consists of several components — a modem, an intermediate-frequency IC, an RF front-end module, two antenna arrays, and an antenna-in-package (AiP), according to System Plus Consulting.

“The rear facing 5G mmWave antenna consists of a 16 passive antenna unit built on an 8-layer substrate,” according to System Plus. “At the side of the phone, an AiP module is integrated in the frame for side communications.”

AiP is required for mmWave. The idea behind AiP is to bring the RF chips closer to the antenna to boost the signal and minimize the losses in systems.

The AiP module consists of a multi-layer patch antenna. A SiP, which resides next to the antenna, incorporates an RF transceiver, a power management IC and passives.

All told, 5G mmWave architectures are complex and difficult to implement. “We need to have a high-density design. 5G requires a high-power power amplifier and power management. So, we need to look at the thermal considerations. We need to look at the design and how to make it more efficient,” said Choon Lee, CTO of JCET, at IMAPS’ SiP conference.

There are other issues, as well. “Between 4G and 5G, there are a number of new frequencies that have been added to the system to be able to address the higher speed requirements. With those additional frequencies, that expands the requirements on the RF front-end portion of the device,” said Mark Gerber, senior director of engineering and marketing at ASE, during a panel discussion at the event. “There are a number of additional components that come in. One of the key challenges is that you can’t continue to expand the space required within the phone. For the phone manufacturers, their key focus is having more space for battery power. To be able to do that, more integration is required, whether that’s combining additional frequencies into a single RF front-end package or module, as well as looking for other ways of simplifying the overall system solution. There are a lot of package solutions in the market that are evolving to try to address some of these challenges.”

5G phones incorporate a multitude of chips with different package types and modules. To develop any package for 5G mmWave, packaging houses requires good components with sound antenna designs. It also requires a good manufacturing and test flow. Materials and substrates are key.

Generally, the chips are available for 5G mmWave. Designing an antenna and integrating it into a package is a fine art. Take the AiP/SiP module as an example.

“At the same radiation efficiency, an AiP needs to be two to four times smaller than the corresponding discrete PCB antenna,” JCET’s Liu said. “In general, the AiP implementation leads to stringent antenna-tuning challenges and thus more RF design margins are warranted. For implementing mmWave AiPs, high-density laminate substrates are often needed.”

Indeed, the substrates play a key role here. “The biggest issues with these advanced systems are the need for thinner substrates, low total thickness variation (TTV), ultra-low defects, strong adhesion, stress control and definitely high-temperature stability for downstream processing such as annealing and metal deposition,” said Kim Yess, executive director of WLP materials at Brewer Science.

The AiP substrates for 5G mmWave are especially complex. “To achieve the performance that they need and the low parasitics, they have to go to some different stack in the substrate design,” Amkor’s Zwenger said. “For mmWave, they have to start looking at very thin dielectrics and low Dk/Df properties. So they’re looking at wafer-level with polyamide thin films.”

And to make matters more complicated, as the value of these packages goes up, there needs to be a way to test these devices. “The introduction of advanced packaging technologies for integrating multiple and/or heterogeneous devices is accelerating along with the continuing scaling in semiconductor manufacturing, where the importance of wafer testing is getting greater than ever before,” said Yohei Sato, general manager at TEL.

SiP is an enabling technology. You won’t see SiPs everywhere, and they tend to get overshowed by chiplets.

But chiplets and SiPs are both viable methodologies. OEMs need all technologies to enable new designs.

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