tag: high-performance computing

Wafer Probe Struggles To Adapt To Multi-Die Assemblies
By Gregory Haley - 13 Jan, 2026 - Comments: 1

Wafer probe, one of the key processes for ensuring reliability in semiconductor manufacturing, is becoming increasingly unreliable in multi-die assemblies and at leading-edge nodes. For much of the semiconductor industry’s history, wafer probe occupied a stable, largely uncontested role in manufacturing. It was understood as a screening step, an electrical checkpoint to identify failing de... » read more

New Panel Production Efforts Target Interposer Costs
By Bryon Moyer - 20 Nov, 2025 - Comments: 0

The rising cost of increasingly large interposers is spurring renewed interest in panel-level manufacturing, which for years has hobbled along due to the massive and collective effort required by the chip industry to change formats. Several companies are developing their own processes, although there is currently no commercial production. And a new consortium called Joint3, spearheaded by Ja... » read more

Distributed Authentication Framework Leveraging Multi-Party Computation In A Scalable Tree-Based Architecture (Univ. of Central Florida, Louisiana State)
By Technical Paper Link - 02 Oct, 2025 - Comments: 0

A new technical paper titled "AuthenTree: A Scalable MPC-Based Distributed Trust Architecture for Chiplet-based Heterogeneous Systems" was published by researchers at University of Central Florida and Louisiana State University. Abstract "The rapid adoption of chiplet-based heterogeneous integration is reshaping semiconductor design by enabling modular, scalable, and faster time-to-market s... » read more

Identifying Divergences in HW Designs For High Performance Computing Workloads (LBNL et al.)
By Technical Paper Link - 15 Sep, 2025 - Comments: 0

A new technical paper titled "Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads" was published by Lawrence Berkeley National Lab (LBNL), Foundation for Research and Technology - Hellas and University of Houston Clear Lake. Abstract "Developing efficient hardware accelerators for mathematical kernels used in scientific applications and machine learning has tra... » read more

Rethinking AI Infrastructure: The Rise Of PCIe Switches
By Vanessa Do - 11 Sep, 2025 - Comments: 0

When thinking of AI, images of futuristic robots or self-driving cars may come to mind. What might not come to mind are the unsung hardware component heroes that are quietly enabling such complex systems. Among these, PCI Express (PCIe) switches might seem to be a boring topic to write about, much less read. But here's the twist—they are nothing short of revolutionary when it comes to empower... » read more

Best Practices and HPC Strategies for Ansys Mechanical
By Ansys - 10 Sep, 2025 - Comments: 0

Mechanical engineers face growing complexity in structural simulations. Modeling intricate geometries, capturing nonlinear material behaviors, and ensuring accurate boundary conditions often push traditional computing resources to their limits. These challenges can lead to longer solve times, convergence issues, and difficulties interpreting results — all of which slow innovation and impact p... » read more

Overview: Ultra Ethernet’s Design and Architectural Advancements (ETH Zurich, Broadcom, HPE et al.)
By Technical Paper Link - 20 Aug, 2025 - Comments: 0

A new technical paper titled "Ultra Ethernet's Design Principles and Architectural Innovations" was published by researchers at ETH Zurich, Broadcom, Hewlett Packard Enterprise, OpenAI, Intel, Microsoft, AMD and Cisco. Abstract "The recently released Ultra Ethernet (UE) 1.0 specification defines a transformative High-Performance Ethernet standard for future Artificial Intelligence (AI) and ... » read more

Best Practices to Optimize Infrastructure for Simulations
By Ansys - 13 Aug, 2025 - Comments: 0

Our Best Practices Guide equips you with expert strategies for leveraging high-performance computing (HPC) to maximize Ansys workload efficiency and overcome common challenges. As simulation complexity increases, a robust computing infrastructure is essential for rapid and large-scale modeling. Modern HPC systems provide: High-core-count CPUs for superior memory and compute perfo... » read more

Chiplet-to-Chiplet Gateway Architecture, A C2C Interface Bridging Two Chiplet Protocols (Peter Grünberg, Jülich Supercomputing Centre)
By Technical Paper Link - 31 May, 2025 - Comments: 0

A new technical paper titled "Modeling Chiplet-to-Chiplet (C2C) Communication for Chiplet-based Co-Design" was published by researchers at Peter Grünberg Institute and Jülich Supercomputing Centre. Abstract "Chiplet-based processor design, which combines small dies called chiplets to form a larger chip, enables scalable designs at economical costs. This trend has received high attention s... » read more

Effects Of Hardware Prefetchers For Scientific Application Kernels Running on High-End Processors
By Technical Paper Link - 14 May, 2025 - Comments: 0

A new technical paper titled "Memory Prefetching Evaluation of Scientific Applications on A Modern HPC Arm-based Processor" was published by researchers at Jülich Supercomputing Centre and KTH Royal Institute of Technology. Abstract "Memory prefetching is a well-known technique for mitigating the negative impact of memory access latencies on memory bandwidth. This problem has become more p... » read more

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