tag: fan-out

Panel-Level Packaging’s Second Wave Meets Engineering Reality
By Gregory Haley - 16 Apr, 2026 - Comments: 0

Key Takeaways Panel-level packaging is arriving not because the engineering is ready, but because wafer-level economics are breaking down. Glass improves the warpage and dimensional stability problems of organic substrates but introduces a different class of failure modes that require materials solutions, not process adjustments. The central challenges of panel-level processing are m... » read more

Redefining Backside Metallization: Low‑Temperature Solutions For HDFO And S‑SWIFT Designs
By Dambi Jo - 19 Feb, 2026 - Comments: 0

As chip performance and integration continue to advance, thermal dissipation control has become increasingly critical not only at the wafer fabrication level but also in the packaging industry. For artificial intelligence (AI) and high performance computing (HPC) applications, the industry is gradually shifting toward 2.5D integration. In response to the growing demand, High-Density Fan-Out (HD... » read more

The Opportunities And Challenges Of FOPLP Technology
By Teck Lee - 23 Oct, 2025 - Comments: 0

Artificial intelligence (AI) has emerged as a major catalyst for innovation and advancement. The growing demand for AI computing power is driving heterogeneous integration toward larger packaging sizes, sparking increased interest in Fan-out Panel Level Package (FOPLP) technology. This article explores ASE’s practices and developments in this area, delving into the technical intricacies and e... » read more

The Rise Of Panel-Level Packaging
By Laura Peters - 24 Jul, 2025 - Comments: 0

An insatiable demand for logic to memory integration for AI and high-performance computing is driving progress toward very large-format packages, which are expected to approach 10 times the maximum reticle size in the next few years. These assemblies are best developed using fan-out panel-level packaging, replacing today’s wafer carrier with a panel. Fan-out packaging enables substantially... » read more

The Race To Glass Substrates
By Gregory Haley - 29 May, 2024 - Comments: 5

The chip industry is racing to develop glass for advanced packaging, setting the stage for one of the biggest shifts in chip materials in decades — and one that will introduce a broad new set of challenges that will take years to fully resolve. Glass has been discussed as a replacement material for silicon and organic substrates for more than a decade, primarily in multi-die packages. But ... » read more

Package Assembly Design Kits: The Future Of Advanced Package Design
By Ruben Fuentes - 23 May, 2024 - Comments: 0

Why should there be an interest in Package Assembly Design Kits (PADK) today? For the most part, it is due to the advancement in the accumulation of files forming the PADK now offering a customized heterogeneous design experience that optimizes the device's intended package performance with complete connectivity verification, DRC, and assembly validation. Another primary reason is the ongoing f... » read more

A Hybrid PLP Technology Based On A 650mm x 650mm Platform
By Eoin O'Toole - 25 Jul, 2023 - Comments: 0

A panel-level (PL) approach to fan-out (FO) packaging has been discussed for several years to reduce the cost of chip-first FO packaging based on redistribution layer (RDL) technology. More recently, multilayer high-density chip-last packages have been introduced for more advanced applications. This technology would also benefit from PL processing for cost reduction. Due to the large package di... » read more

Repurposing Josephson Junctions At The Cell Boundaries For Fan-out (UCSB)
By Technical Paper Link - 16 Dec, 2022 - Comments: 0

A technical paper titled "Low-Cost Superconducting Fan-Out with Repurposed Josephson Junctions" was published by researchers at UC Santa Barbara.  The paper received an award at the Applied Superconductivity Conference in Oct 2022 and was highlighted in this UCSB news article. Abstract: "Superconductor electronics (SCE) promise computer systems with orders of magnitude higher speeds and lo... » read more

Which Foundry Is In The Lead? It Depends.
By Ed Sperling - 26 Oct, 2022 - Comments: 2

The multi-billion-dollar race for foundry leadership is becoming more convoluted and complex, making it difficult to determine which company is in the lead at any time because there are so many factors that need to be weighed. This largely is a reflection of changes in the customer base at the leading edge and the push toward domain-specific designs. In the past, companies like Apple, Google... » read more

Technology Advances, Shortages Seen For Wire Bonders
By Mark LaPedus - 17 Feb, 2022 - Comments: 2

A surge in demand for IC packages is causing long lead times for wire bonders, which are used to assemble three-fourths of the world’s packages. The wire bonder market doubled last year, alongside advanced packaging’s rise. Wirebonding is an older technology that typically flies under the radar. Still, packaging houses have multitudes of these key tools that help assemble many — but no... » read more

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