A Hybrid PLP Technology Based On A 650mm x 650mm Platform

Assembly of multiple fan-out wafers or subpanels on a carrier panel with reduced cost in the RDL process.


A panel-level (PL) approach to fan-out (FO) packaging has been discussed for several years to reduce the cost of chip-first FO packaging based on redistribution layer (RDL) technology. More recently, multilayer high-density chip-last packages have been introduced for more advanced applications. This technology would also benefit from PL processing for cost reduction. Due to the large package dimensions, applications such as an application processor (AP) or multichip module (MCM) will have greater benefits than the smaller power management integrated circuit (PMIC), transceiver or audio codec applications typical of chip-first FO packaging.

The known technical challenges with panel-level fan-out (PLFO) packaging range from die-shift over the full panel, through warpage of the panel along the process flow, which limits the number of redistribution layers, to controlling the total thickness variation (TTV) during the panel-level back-grind processes. Commercial aspects such as capital expenditures on panel-level equipment and difficulty in filling a panel line are the main financial considerations.

A 650 mm x 650 mm PLFO technology will be presented which enables assembly of four 300 mm round or 300 mm square fan-out subpanels on a carrier panel. This technology enables the reutilization of the reconstitution and die / package-level processing equipment, focusing the panel processing where the greatest cost benefit can be achieved in the redistribution layer process. The use of a carrier panel minimizes the warpage, permitting implementation of more RDLs without impacting processability. The reconstitution portion of the flow is performed on the smaller form factor, minimizing die-shift considerations on the large panel. The same panel equipment and infrastructure can also be used for chip-last PLFO or high-density, high-quality coreless substrates. Process flow details will be shared based on a PLFO pilot line.

Component level reliability results on a chip-last fan-out test vehicle will be shown as well as comparative cost modelling on chip-first PLFO vs 300 mm fan-out wafer for both chip-first and chip-last fan-out packages.

To overcome the concern of filling a panel line, a flexible panel technology has been developed which can be employed in a wide range of package technologies.

Technology application:

  1. Wafer Level Chip Scale Package (WLCSP) – 300 mm, 200 mm, 150 mm [1]
  2. Wafer Level Fan-Out (WLFO) – Die first, redistribution layer (RDL) first [2], [3]
  3. System-in-Package (SiP) [4]

Fig. 1: Examples of wafers and panels assembled on a 650 mm x 650 mm glass panel.

The Hybrid Panel Level Package (Hybrid PLP) Technology (HPLT) is based on large format 650 mm x 650 mm panel. This panel format permits the processing of four 300 mm wafers or square panels, nine 200 mm wafers or 16 150 mm wafers.

The process flow after assembly on the glass panel is effectively the same for WLCSP, die first WLFO wafers, or for panel-level fan-out (PLFO) panels, as illustrated in figure 1. Descriptions for WLCSP and WLFO process flows are shown in figure 2.

Fig. 2: Process flows for WLCSP and die-first fan-out.

The wafer or sub-panel is assembled on a coefficient of thermal expansion (CTE) matched, large-format glass panel by means of a temporary bonding adhesive. The dielectric layers are applied in a panel-by-panel process appropriate to ensure an excellent layer uniformity. Exposure is performed on a panel-level stepper equipment – the alignment being performed on an individual wafer or sub-panel basis. The developer process is performed once again on a panel-by-panel basis. Curing is performed in an atmospherically controlled curing oven. The bill of materials (BOM) was selected to provide identical mechanical and chemical characteristics of redistribution layers processed on the wafer process line. For the die last or RDL first application of this technology, the process flow is inverted, as shown in figure 3.

The RDL layers are built up directly on the glass panel, starting with the under-bump metallization layer (UBM) and proceeding from the top RDL layer to the bottom RDL layer with the respective interlayer dielectrics. After completion of the bottom RDL layer, an additional UBM layer is required to enable flip-chip assembly of the die onto the RDL stack. Subsequent to the flip-chip assembly, a mold underfill (MUF) process or, for finer pitch applications, a capillary underfill (CUF) and mold process can be used to complete the encapsulation of the device. The glass panel can then be debonded from the molded device. Currently available flip-chip and mold equipment require that the glass panel must be subdivided into smaller dimensions, which means that the glass panel cannot be reused in this application. This limitation may be overcome by using panel-level flip-chip and molding.

Fig. 3: Process flow for RDL first applications.


HPLT focuses on the most expensive elements of any redistribution technology – the redistribution layers themselves. The process steps which will have a significant cost benefit of massively parallel processing are performed on a panel basis. This includes coating and developing of dielectric and photo resist layers, exposure of the dielectric layers and photo resist layers, curing of the dielectric layers, physical vapor deposition of the seed layers, electrochemical deposition, photo resist strip and chemical wet etch of the remaining seed layer.

This strategy yields significant cost benefits for all the package technologies involved. To correctly access the potential cost gains achievable using this technology, cost modeling was performed for the different applications. The most straightforward comparison is possible with WLCSP applications, since all considerations of die or packages dimension may be ignored as only the wafer-level processing costs are relevant for the comparison.

Fig. 4: Cost comparison for the redistribution layers performed on wafer versus panel-level designs.

What can be observed from the cost comparison in figure 4 is that a significant cost advantage can be achieved and that the cost benefits improve with smaller wafers as the ratio of wasted area to useful area decreases.

For the Fan Out application, the die first application is considered as the die last is too dependent upon the subsequent assembly processes. For the die first application, the comparison is 3-fold between WLFO in 300 mm wafer produced on a 300 mm wafer processing line, 4 x 300 mm round wafers processed and assembled on a 650 mm panel and finally 300 mm square panels assembled on a 650 mm panel, as shown in figure 5.

Fig. 5: Cost comparison for the redistribution layers performed on wafer versus panel-level designs for die-first applications.

The cost simulation performed showed a significant benefit of processing four 300 mm round wafers assembled on the large format panel. However, the area utilization achieved using four 300 mm square sub-panels assembled on the glass panel leads to further significant potential gains.

Test vehicle description

To demonstrate the capabilities of the technology, a six-metal layer RDL-first test vehicle (TV) was selected.

Fig. 6: Test vehicle structure.

The multi-RDL structure was built up on a 650 mm x 650 mm glass panel using photolithographic methods, as described previously in figure 3. After completion of the RDL processing up to the die side under-bump metallization (UBM), the glass panel was sectioned into smaller pieces matching the capability of the subsequent assembly equipment. Flip-chip die placement was performed, and the dies were soldered via mass reflow.

The subsequent mold process was applied to encapsulate the assembled die and also to act as a mold underfill. Laser debond was employed to dissociate the glass RDL support from the encapsulated package. The individual packages were separated using mechanical blade dicing.

The minimum critical dimensions of the redistribution layers were 5-µm line space and 5-µm line width. The UBM layers had a nominal thickness of 7 µm, all 4 redistribution layers had a nominal thickness of 5 µm and the dielectric layers’ thickness was 5 µm. The inline measurement data obtained related to RDL metal layers is shown in table 1, with all values well within the defined specification.

Table 1: Metal layer related data.

One concern with a large format panel with multi-RDLs is warpage caused by the curing of the different dielectric layers and the CTE mismatch between the glass and the dielectric. Before starting the activities, a finite element simulation was performed to assess the expected warpage. The stack simulated was a four RDL layer structure with five dielectric layers. Three types of glass with three different CTEs ranging from CTE well matched with silicon (Si), CTE well matched with die-first Fan Out and an intermediate CTE value. Two panel thicknesses were considered depending upon the CTE.

Fig. 7: Panel warpage after 1L RDL and 4L RDL.

As expected, the simulation shows an accumulation of warpage effects with additional RDLs (metal + dielectric).

Fig. 8: Panel warpage based on two panel thicknesses and three CTEs.

The simulated warpage and the measured warpage agree well in tendency, however, the magnitude of the warpage observed was significantly lower than the simulation predicted and far from the equipment handling specification shown in the graph. The discontinuities in the dielectric film were most likely the cause of the difference.

After completion of the subsequent assembly steps, mechanical cross sections were performed to analyze the layer structure compared to the nominal values and as a first assessment of package integrity.

Fig. 9: Layer thickness measured in cross section at 0 hours.

Singulated units were subjected to a series of reliability testing. The principal focus of this reliability assessment was layer adhesion and package integrity. Results of the reliability tests performed are shown in table 2. All results were positive with no fails observed after stress tests.

Table 2: Component level reliability results.


This post has presented a novel panel level packaging technology platform. The flexibility of the platform for use in WLCSP, WLFO and PLFO designs, both in die-first and die-last configurations, has been shown. Results of a multilayer die-last test vehicle have been presented displaying excellent reliability with a bill of materials identical to the equivalent wafer level package. Cost modeling results demonstrated the significant gains achievable with this technology.

Warpage concerns for multilayer RDL structures raised by simulation were not confirmed with inline data – the data showing a significant handling margin. Reliability assessment proved the package integrity of die-last packages processed using the 650 mm x 650 mm panel format.

Based on the results to date, further studies are encouraged to fully explore the manufacturability and reliability of this packaging technology.


The authors would like to acknowledge the contribution made by Nathan Whitchurch in performing the warpage simulation and thank the ATK5 wafer level development team for their support in this study.


[1] P. Garou et al., “Wafer level chip scale packaging (WL-CSP): an overview,” IEEE Transactions on Advanced Packaging (Volume:23, issue 2, May 2000, PP. 198 – 205, DOI: 10.1109/6040.846634.

[2] M. Brunnbauer, E. Fürgut, G. Beer, T. Meyer, “Embedded Wafer Level Ball Grid Array (eWLB),” 2006 8th Electronics Packaging Technology Conference. 6-8 Dec. 2006, DOI: 10.1109/EPTC.2006.342681.

[3] Norikazu Motohashi, Takehiro Kimura, Kazuyuki Mineo, Yusuke Yamada, Tomohiro Nishiyama, Koujiro Shibuya, Hiroaki Kobayashi, Yoichiro Kurita, Masaya Kawano, “System in wafer-level package technology with RDL-first process,” 2011 IEEE 61st Electronic Components and Technology Conference (ECTC) DOI: 10.1109/ECTC.2011.5898492.

[4] T. Wakabayashi, “FOWLP technology as wafer level system in packaging (SiP) solution,” 2017 International Conference on Electronics Packaging (ICEP), 19-22 April 2017, DOI: 10.23919/ICEP.2017.7939429.

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