Multi-physics simulation and new reflow options help keep a lid on warpage.
Warpage of dies, redistribution layers, and interposers is a growing problem in multi-chiplet packages, and it can have a dramatic impact on the behavior and reliability of these devices.
Multiple factors contribute to warpage, including larger chip sizes, severe thinning of the silicon substrate, temporary bonding and debonding processes, and scaling of bump pitch and size. Each of these can impact the reliability of the overall structure. In addition, chiplets undergo multiple thermal cycles during manufacturing and operation, which can lead to chip delamination, cracking, or even missing bumps in advanced packages.
“The bump array is the most important part when it comes to warpage, because you can create voids or even a crack – physical disconnections that will be detrimental to your system,” said Lang Lin, principal product manager of 3D-IC multi-physics simulation and hardware security at Synopsys.
Microbumps must meet strict planarity requirements. Any stresses exerted during reflow, for instance, have a tendency to induce warpage and bowing behavior. Some of the strategies chipmakers and module designers are using to mitigate bow and warpage include:
The power of multi-physics simulation
Multi-physics simulation is being employed early on in advanced package designs. Finite element modeling (FEM) makes it possible to simulate the physical world without the expense, time, or risk of building physical prototypes. FEM predicts how real-world forces, vibration, heat, and other physical effects will impact a package, helping to identify potential weak points and assess how and when a product fails. FEM is used in conjunction with test structures and then with the final assembled module.
Thermal effects are especially relevant as chipmakers continue to package more dies closer together. FEM simulates heat transfer and temperature distribution, allowing engineers to assess thermal management strategies, identify hot spots, and predict stress, strain and warpage caused by thermal expansion mismatches (TCE) between different materials. Silicon has a TCE of 2.6 ppm/°C; gallium arsenide’s is 6.86 ppm/°C; copper’s TCE is 16.7 ppm/°C; tin-lead solder’s TCE is 27 ppm/°C, and FR4 substrates have a TCE of 11 to 17 ppm/°C.
“You can look at a multi-chiplet system as a sandwich with an interposer, then die 1, die 2, etc., then molding, thermal interface materials, and the heat sink,” said Lin. “One way to minimize warpage is to have a gradual tapering of CTE of the materials, because if you have too big a CTE difference between any two layers, you create an interface with large warpage, so it’s best to balance these properties vertically.”
Another material property that significantly influences warpage behavior is Young’s modulus, a measure of its elasticity or stiffness. For example, the modulus of single-crystalline silicon is 130 GPa in the <100> orientation, but 188 GPa in the <111> direction. This difference influences the electrical properties of devices built on silicon and is a key determinant in wafer selection.
Potential delamination during wafer thinning
Wafer thinning is becoming common practice for a variety of devices, but especially mobile applications that demand ultra-thin profiles. Advanced packaging of 2.5D and 3D demands thinning of silicon down to less than 100µm.
Temporary bonding materials between the carrier and device wafer must withstand strong centrifugal forces during backside grinding. A recent project by Nader Jedidi, research and development engineer for 3D Integration, and colleagues at imec evaluated Brewer Science’s VersaLayer system during backgrinding. [1] “Depending on the multilayer BEOL stack (dielectric/metal materials, thicknesses, design) and the process conditions, typically deposition and baking temperature(s), device silicon wafers, heading to thinning, might be significantly warped. Coefficients of thermal expansion mismatch between the substrate and the stack dielectric and metal layers is one of the most important factors driving the wafer shape. The deposition, or growth of layers with large CTE mismatch, large Young’s moduli and thicknesses (i.e.: a thick and stiff material), will definitely cause the wafer to bow significantly,” according to the authors.
The project confirmed that non-warped wafers will not delaminate during grinding. “At grinding, while the substrate thickness is decreasing, the flexural rigidity of the substrate keeps diminishing and the wafer bow increasing. For the top wafer to remain bonded to the carrier, the TBM/RL (temporary bonding material/release layer) system is required to compensate for an increasingly larger debonding moment. Below a certain silicon thickness, the latter will be large enough to overcome the adhesion forces within the weakest interface, leading to the debonding/delamination of the top wafer, in the edge area.”
Finally, imec’s work confirmed that three variables are key determinants of wafer delamination during backside silicon grinding — the silicon target thickness, the wafer bow, and the adhesion strength of the release layer to the BEOL stack under the loading conditions of the grinding process. “For a fixed stack top layer (SiO2, SiCN, SiNx, etc.) and a fixed RL/TBM system, setting the silicon target thickness, typically ≤100μm, amounts to setting the process window for the bow, or alternatively, the maximum bow allowed for a delamination-free thinning.”
Lidded vs. lidless assembly
Some package designers employ a lid on the semiconductor package to spread heat from the die/TIMs to the heat sink, but there are advantages and disadvantages to using lids. They make the package thicker, and in some cases don’t dissipate heat as effectively as lidless solutions, where the chip interfaces more directly with the heat sink.
“There is the whole question of lidded versus lidless design. Some customers prefer the lidless because the lid material is different from that of the silicon and the heat sink. The stiffness of that lid is not well-positioned to actually hold the whole multi-chip system,” said Synopsys’ Lin.
When lids are needed, they can be fabricated from materials such as Kovar, Alloy 52 or ceramics (for hermetic sealing), or nickel-plated copper. In fact, all-metal packages are commonly used in high-performance computing/HBM applications.
In packages, more than 90% of the heat dissipates out of the top of the chip, through the package, to a heat sink, which is typically anodized aluminum-based with vertical fins. Thermal interface materials (TIMs) with high thermal conductivity are placed between the chip and package to help transfer heat.
TIMs are available in various form factors, enabling the filling of tiny gaps within the package. MinJae Kong, director of process/material research and colleagues at Amkor Technology Korea, recently investigated the effects of increasing the silver content in indium metal TIMs on package warpage using a flip-chip lidded BGA. [2] “Indium exhibits excellent thermal conductivity, high adhesion to devices, and durability. Therefore, indium metal thermal interface materials (TIMs) are expected to play an important role as thermal management solutions in high-performance semiconductors and electronic devices,” Kong said.
Pure indium cannot be used because it melts at solder reflow temperatures (250°C). Based on reliability testing, warpage assessments by shadow moiré, and warpage and simulation results from finite element analysis, the Amkor study revealed that reducing the silver content in the indium alloys results in greater TIM coverage degradation and increased package and die warpage at high temperatures.
“Considering these findings, it may be advantageous in terms of TIM coverage to use an indium alloy with a higher silver content for FCLBGA packages undergoing solder reflow. However, this assumption is only valid for FCLBGA packages with large warpage deflection at room temperature and high temperature. Future research on each alloy will need to focus on practical measures to further reduce package warpage and maintain TIM coverage,” Kong said.
Mass reflow, TCB, reverse laser-assisted bonding
There are several options for reflow soldering, each with its own pros and cons. Mass reflow is the original and least expensive method, yet its performance is limited when it comes to large/thin substrate packages with fine bumps (<45µm lines/spaces).
Thermocompression bonding (TCB) has been in production for years. It works by exerting both downward pressure and high temperature (250°C to 400°C, depending on metal) on the assembly, so warpage is improved relative to mass reflow. But tool productivity is lower than that of mass reflow or reverse laser-assisted bonding (R-LAB). TCB’s high pressure and temperature cause metal-metal intermixing and bonding.
Laser-assisted bonding depends on localized heating at the critical interface between metals. In recent years, Amkor engineers developed reverse LAB to locally heat bumps through an underlying stage block that is transparent to the laser wavelength. Over the last year, the company began exploring laser-assisted TCB, which is compatible with applications using backside metalization and chiplet module bonding (molded silicon die) bonding on a substrate.
“Reverse laser compression bonding (R-LTC) is essentially combination of R-LAB and TCB that targets high and large warpage modules. One advantage of R-LTC is it helps to minimize thermal stress to the die because bump wetting is mainly done by the reverse laser heating,” said Seokha Na, senior director or product development at Amkor Technology Korea. [3] The bond head controls the standoff height, alignment, and die tilt by combining temperature, pressure, and force. It transfers less heat to the module than TCB does.
Fig. 1: Reverse laser compression bonding combines the localized heating of lasers with the bond head control of standoff height, alignment and die tilt. Source: Amkor
Warpage with embedded die structures
Power-efficient electronic devices often involve one or more dies embedded in laminated build-up layers to achieve high performance and good heat dissipation in a thin and small footprint. ASE engineer Wei-Hong Lai and colleagues evaluated strip-level warpage control in Semiconductor Embedded in Substrate (SESUB) technology. [4]
“A finite element method (FEM) was constructed and experimentally benchmarked for warpage validation. Taguchi design response shows that substrate resin layer with low CTE property and thinner die thickness as the key factors influencing warpage,” according to the authors. Warpage of the strip (see figure 2) was measured at room temperature and high temperature using 3D digital image correlation techniques.
Fig. 2: FEM was performed using a quarter of the strip. Source: ASE
“The finite element method (FEM) is a preferred approach for numerical model and analyzing strip-level warpage. The substrate structure was considered equivalent copper ratio effect and layer-by-layer stack-up. Embedded die placement was also distributed into the strip layout based on design rule,” they said
Interestingly, the warpage magnitude was about 3X greater at room temperature than at 260°C. Using the Taguchi method, certain conditions heavily influenced warpage, including die thickness, which improves stiffness in the strip, using low CTE and low modulus materials in the substrate resin, lamination dielectric, and solder mask. By selecting optimal materials and structuring the layout with copper, balancing as well as using a thicker top resin than bottom resin, helped reduce warpage by 50%.
Conclusion
Finite element modeling has long been used to optimize package layouts, but it is now being employed at smaller scales to best understand how thin films will interact through processing and multiple thermal cycles.
To prevent wafer delamination during thinning processes stretching down to only 50 microns of silicon, three factors especially influence warpage — the die thickness remaining, high CTE mismatch, and high Young’s modulus, which induce more wafer bowing. Optimizing these parameters helps to prevent delamination during thinning.
Bonding techniques, including thermocompression bonding, reverse laser-assisted bonding, and a relatively new reverse thermocompression bonding (R-LTC), may all be considered in advanced packaging. R-LTC may offer better alignment and lower standoff thickness, important issues in multi-chip packaging.
Warpage has and will require control measures during assembly, including reflow tooling selection, as well as selecting compatible CTE materials and only gradual CTE changes in the stack. Novel materials with low CTE and low Young’s modulus help improve wafer and die bowing.
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