tag: wafer thinning

TSV Complexity Leads To Manufacturing Bottleneck
By Laura Peters - 22 Apr, 2026 - Comments: 1

Key Takeaways: Through-silicon vias are the biggest enabler of 3D chip stacking and chip-to-PCB connections through silicon interposers. The AI boom is causing HBM and advanced assembly shortages, straining the supply chain. Optimization around etch, fill and reveal help reduce TSV cost. Through-silicon vias (TSVs) provide essential interconnects between DRAM dies inside hig... » read more

HBM4 Sticks With Microbumps, Postponing Hybrid Bonding
By Bryon Moyer - 13 Jan, 2026 - Comments: 0

The next generation of high-bandwidth memory, HBM4, was widely expected to require hybrid bonding to unlock a 16-high memory stack. A JEDEC move made that unnecessary with this generation, but it’s merely a postponement, not a cancellation. HBM has been in high demand for AI in data centers — especially for training. Data movement dominates energy consumption, and high-bandwidth memories... » read more

Mitigating Warpage In Multi-Chiplet Systems
By Laura Peters - 22 Sep, 2025 - Comments: 0

Warpage of dies, redistribution layers, and interposers is a growing problem in multi-chiplet packages, and it can have a dramatic impact on the behavior and reliability of these devices. Multiple factors contribute to warpage, including larger chip sizes, severe thinning of the silicon substrate, temporary bonding and debonding processes, and scaling of bump pitch and size. Each of these ca... » read more

The Other Side Of The Wafer: Transistor Channel Stress In Backside Power Delivery Networks
By Sam Sarkar - 17 Apr, 2025 - Comments: 0

As transistor scaling has moved to the angstrom era (18A, 14A, etc.), the issues of interconnect resistance (IR), IR drop, and power loss are becoming more severe. Traditionally, signal lines and power lines are fabricated on the same side of the wafer as the active device. But fabricating everything on one side of the wafer can create a shortage of space and resources at the interconnect la... » read more

The Rise Of Thin Wafer Processing
By Laura Peters - 20 Mar, 2025 - Comments: 0

The shift from planar SoCs to 3D-ICs and advanced packages requires much thinner wafers in order to improve performance and reduce power, reducing the distance that signals need to travel and the amount of energy needed to drive them. Markets calling for ultrathin wafers are growing. The combined thickness of an HBM module with 12 DRAM dies and a base logic chip is still less than that of a ... » read more

Electrifying Everything: Power Moves Toward ICs
By Gregory Haley - 23 Jan, 2025 - Comments: 1

As electronic systems grow increasingly complex and energy-intensive, traditional power management methods — centered on centralized systems and external components — are proving inadequate. The next wave of innovation is to bring power control closer to the action — directly on the chip or into a heterogeneous package. This change is driven by a relentless pursuit of efficiency, scala... » read more

Hybrid Bonding Makes Strides Toward Manufacturability
By Laura Peters - 28 Oct, 2024 - Comments: 0

Hybrid bonding is gaining traction in advanced packaging because it offers the shortest vertical connection between dies of similar or different functionalities, as well as better thermal, electrical and reliability results. Advantages include interconnect scaling to submicron pitches, high bandwidth, enhanced power efficiency, and better scaling relative to solder ball connections. But whil... » read more

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