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WLFO For High-Performance Low-Cost Packaging Of RFMEMS-CMOS


Navigating the trade-offs between performance, size, cost and reliability can be a challenge when considering integrated circuit (IC) packaging and the end-application. The integration of micro-electromechanical systems (MEMS), either monolithic or heterogeneous, introduces yet another level of complexity that has only recently been a major focus of multi-device packaging. Wafer-level fanout (W... » read more

New RDL-First PoP Fan-Out Wafer-Level Package Process With Chip-to-Wafer Bonding Technology


Fan-Out Wafer-Level Interposer Package-on Package (PoP) design has many advantages for mobile applications such as low power consumption, short signal path, small form factor, and heterogeneous integration for multifunctions. In addition, it can be applied in various package platforms, including PoP, System-in-Package (SiP), and Chip Scale Package (CSP). These advantages come from advanced inte... » read more

The Race To Much More Advanced Packaging


Momentum is building for copper hybrid bonding, a technology that could pave the way toward next-generation 2.5D and 3D packages. Foundries, equipment vendors, R&D organizations and others are developing copper hybrid bonding, which is a process that stacks and bonds dies using copper-to-copper interconnects in advanced packages. Still in R&D, hybrid bonding for packaging provides mo... » read more

Fan-Out Wafer-Level Packaging And Copper Electrodeposition


By Steven T. Mayer, Bryan Buckalew, and Kari Thorkelsson As integrated circuit designers bring more sophisticated chip functionality into smaller spaces, heterogeneous integration, including 3D stacking of devices, becomes an increasingly useful and cost-effective way of mixing and connecting various functional technologies. One of the heterogeneous integration platforms gaining increased ac... » read more

Material Solutions For FOWLP Die Shift And Wafer Warpage


By Shelly Fowler Today's fan-out wafer-level packaging (FOWLP) processes use organic substrates composed of epoxy mold compound (EMC) created using a thermal compression process. EMC wafers are a cost-effective way to achieve lower-profile packages without using an inorganic substrate to produce chip packages that are thinner and faster without the need for interposers or through-silicon-via... » read more

Panel Fan-out Ramps, Challenges Remain


After years of R&D, panel-level fan-out packaging is finally beginning to ramp up in the market, at least in limited volumes for a few vendors. However, panel-level fan-out, which is an advanced form of today’s fan-out packaging, still faces several technical and cost challenges to bring this technology into the mainstream or high-volume manufacturing. Moreover, several companies are d... » read more

Solving Fan-Out Wafer-Level Warpage Challenges Using Material Science


Now more than ever we’re finding that semiconductor process engineers are turning to material scientists to help find solutions for their most complex challenges. Currently, they are looking for ways to improve fan-out wafer-level packaging (FOWLP), one of today’s hottest technologies for heterogeneous integration. Often, with these new advanced solutions come challenges that can impact ... » read more

Extending The IC Roadmap


An Steegen, executive vice president of semiconductor technology and systems at Imec, sat down with Semiconductor Engineering to discuss IC scaling and chip packaging. Imec is working on next-generation transistors, but it is also developing several new technologies for IC packaging, such as a proprietary silicon bridge, a cooling technology and packaging modules. What follows are excerpts of t... » read more

Fan-Out Wafer Level eWLB Technology As An Advanced System-in-Package Solution


System-in-Package (SiP) technology continues to be essential for higher integration of functional blocks to meet the ever demanding market needs with respect to smaller form factor, lower cost and time to market. A typical SiP incorporates all or some form of Fan-Out Wafer Level packaging, wire bonding or flip chip that serves a multitude of applications such as optoelectronics, RF, power ampli... » read more

Advanced Packaging’s Progress


Shim Il Kwon, CTO at STATS ChipPAC, sat down with Semiconductor Engineering to discuss the current and future trends of chip packaging. What follows are excerpts of that conversation. SE: The outsourced semiconductor assembly and test (OSAT) vendors provide third-party IC-packaging and test services. What are the big challenges for OSATs today? Shim: The OSAT market is very competitive, w... » read more

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