The March Toward Chiplets

The benefits of heterogenous integration are well understood, but getting there isn’t easy.


The days of monolithic chips developed at the most advanced process nodes are rapidly dwindling. Nearly everyone working at the leading edge of design is looking toward some type of advanced packaging using discrete heterogeneous components.

The challenge now is how to shift the whole chip industry into this disaggregated model. It’s going to take time, effort, as well as a substantial realignment of companies, technology, and focus. As the benefits of scaling continue to dwindle at each new node, chipmakers are looking toward architectures and customization to improve performance and reduce power. Systems-in-package, 3D-ICs, 2.5D, and fan-outs are all viable options. But the biggest players are looking to chiplets to help provide some level of mass customization, where features can be added like LEGOs and work as expected.

“We are in a new era,” said William Chen, ASE fellow. “In the past, we used to think about three segments — the users, the fabs, and the packaging people in between. Now we have to think about a much broader ecosystem. We need equipment, we need design tools, and all of them have to work together. This is happening, because everyone has a common goal, which is heterogeneous integration, stacking chiplets, and customizing solutions. It used to be that we only had one way to go forward. Now we have multiple ways. So we can find the best combination for a particular use case, and that may be different than for another use case.”

Fig. 1: 2.5D and 3D-IC packaging. Source: ASE

Chen’s view is being echoed throughout the industry. “This is another tool in the toolbox,” said Kim Arnold, chief development officer at Brewer Science. “It’s not only the flexibility in how to turn things on and off and make them fit together, but also designing different ways to make things fit together. That’s Intel’s philosophy, and they’re not alone in that. It’s how it’s going to have to work to create these packages that fit together to come up with the whole system. That’s the piece that’s challenging.”

Applications are driving technology solutions. “The industry is now looking at intelligent integration solutions,” said Jean-Rene’ Lequepeys, CTO and deputy director of Leti. “Using the current versions of SOITEC’s SmartCut technology, for instance, there are going to be combinations like InP on silicon, or GaN, SiC, SOI, etc., to satisfy the application.”

Nearly everyone involved sees this as a process, not a quick change, and one filled with significant hurdles. “The ecosystems for chiplets are actually being formed,” said Indong Kim, vice president of product planning at Samsung Electronics. “Given what’s happened with Moore’s Law, there has been a lot of investment and interest in making that work. I don’t know if anybody really has a silver bullet to that solution yet. We are monitoring the situation. But it’s not just a single technology. You need R&D for packaging innovations, as well as the interfaces for the various IPs. You also must be able to figure out which are the known good dies, and make sure that you have the proper yield. There are an endless number of questions that we’re trying to answer.”

Material issues
Among the challenges is how to integrate chips developed at different nodes and using different substrates or dielectric films, which may react differently to heat or age at different rates under different conditions, including where these various chiplets are placed within a package.

“One of the key trends is about new materials,” said Shay Wolfling, CTO at Nova. “In the past, I would stabilize the material in my lab, and once it went in line, I didn’t need to measure anything. I would measure it on some blank wafer to make sure everything is in control. But the importance of the materials and structure is now so significant that every atom counts. With every change in the process, if you increase the temperature too much — even little changes in your anneal process — you change the material properties. So you need to monitor them. At the edge of the wafer there could be different density, which will behave differently.”

Different materials also make it harder to predict how these various pieces will work with other components.

“The key is consistent characterization,” said Mike McIntyre, director of software product management at Onto Innovation. “The reason you’re going to chiplets is to gain the flexibility of yield and performance. So while materials like antimony and bismuth are good for communication, I don’t want to build a CPU with those materials because it’s going to impact my transistor performance. So I’m building chiplets based on the technology that’s most appropriate for that chiplet. From an economic standpoint, I don’t see the number of chiplets going down. If anything, the numbers will go up.”

Design issues
Layout is critical to the functioning of these devices, and it involves a number of factors, such as use cases, coefficients of thermal expansion, various types of noise, and how well they will perform over time and within a given power budget.

“The current status of the industry is like chiplets, where you have partitions that can be made separately by separate companies and then they talk together,” said Eric Beyne, senior fellow, vice president of R&D, and director of the 3D System Integration Program at imec. “It works, but it does introduce a PHY interface and it doesn’t reduce latency. So you can only do that for non-critical time issues, like L3 cache, but not L2 cache. So if you want to go inside of your chip and go deeper in the hierarchy toward the core itself — let’s say L1 or L2 cache, then you can split the design. But you’re not going to use an off-the-shelf memory for that. It’s going to be co-designed with your chip. So the EDA tools need to be able to handle the PDK of your different layers, all at once during place-and-route. That’s something we’ve been actively working on with Cadence, and they have released actually place-and-route tools for meeting this kind depth for what I call a 3D SoC. From a design perspective, there are a lot of challenges, because you have to do the place-and-route in in multiple layers. Tools normally don’t work that way, so you have to guide the tool and, say, put memory on one level and logic on another. And then you optimize the interconnect.”

Interconnects rank high on the list of challenges, as well. Chiplets need to connect individual dies to each other and finally to the substrate in a package. The Universal Chiplet Interconnect Express (UCIe) standard, released earlier this year, is a step in this direction. It combines CXL and PCIe protocols. However, this approach has a way to go before being truly “universal.”

The physical layer is the starting point. “You have to get the PHYs right,” said Michal Siwinski, chief marketing officer at Arteris IP. “You need to make sure the physical level works. This is where we are seeing more of the bigger players coming together. We will need one or two standard ways for the industry to hook everything together. But to truly make it all work, you have be able to do this in a standardized, repeatable fashion.”

Integration and connection issues
While integrating multiple chips into a package has been around since the 1980s, breaking a modern chip down into core parts and then integrating them together into a package is a lot harder than the old multi-chip modules.

“One of the big benefits of going to monolithic integrated circuits was that the number of connections went down. You just had the I/Os at the edge, so the reliability shot up,” said Marc Swinnen, director of product marketing, Ansys. “But now we’re going to heterogeneous integration. We’ve been monolithic so long that we’ve forgotten that interconnections aren’t really a good thing, and now we’re going back to millions of tiny bump connections. What’s the reliability on that going to be?”

These considerations can affect every aspect of production, from design through how to approach inspection. “We are seeing lots of interest in chiplets,” said Yervant Zorian, chief architect and fellow at Synopsys. “In many cases they are communicating via PHYs. If it’s logic-to-logic communication, they’re using UCIe. If it’s logic-to-memory chiplets, they’re using HBM, but in both cases you need engines for diagnosing, repairing, and monitoring. In the past we used to rely on test and repair only for memories. Today we’d like to look in advance. We don’t want to wait until the chip fails. So that’s why we want monitoring. It’s preventive maintenance. By monitoring, you can see the degradation over time and you will know when something will happen.”

Fig. 2: The shape of things to come — 3D-IC. Source: Synopsys

This is one of the reasons foundries and IDMs are building their own ecosystems. TSMC, for example, has developed a 3DFabric, which can be used for both front-end and back-end packaging. To create a commercial chiplet marketplace, where chiplets from multiple vendors are developed according to standards that enable them to be truly plug-and-play will be much more difficult, and according to some industry insiders, could take the better part of a decade.

“When we build these multiple chiplet-based systems, we need to validate that the conductivity between chiplet A to chiplet B to chiplet C throughout the packaging is all connected correctly,” said John Park, product management director for IC packaging at Cadence. “In the IC world, we call that LVS (layout versus schematic), but a similar concept needs to be applied at the foundry packaging level. For a single die, it’s not that complex, but when you move to multiple chips or chiplets in a FOWLP, you need to validate that everything is correctly connected together. It’s very important for people when they put together design flows to think about it early on.”

On top of that, chiplets are subject to the other challenges of heterogenous structures, such as thermal and mechanical stress.

“You have a single chip, it’s more uniform in temperature,” said Swinnen. “But when you have multiple chips on an interposer, you have differential temperatures and they’re going to expand differently. You can get warpage and with microbumps being so small now, their reliably is at risk. We know stress impacts electrical performance of transistors, and even wires. The differential stress will affect the electrical parameters differentially.”

But there’s still more. Chiplets face another familiar challenge — die shift. “Solving die shift is critical for moving from beyond a single die or two to a world where you can support multiple chips or chiplets,” said Cadence’s Park. “The more dies you have, each one gets slightly shifted by a degree or two, and then you put six together and nothing connects anymore.”

John Parry, electronics industry manager at Siemens EDA, pointed to similar issues. “You’ve got multiple challenges that all interact with one another. What might be a good solution from the point of view of one die, actually makes the situation on the next die worse. If I can conduct more heat out of one chiplet into the substrate, it makes that chip cooler, but it raises the temperature of the substrate, which raises the temperature all the other chips. It’s a Whac-A-Mole problem where you no sooner solve one problem than it gives you a problem in another area.”

Still, there is good news. Chiplets may help the industry better cope with thermal problems that have become persistent issues with advanced architectures, since many existing approaches are sub-optimal.

“Thermal throttling is absolutely a mechanism to keep temperatures down,” said Nathan Whitchurch, senior staff engineer, Amkor. “But nobody likes doing that because all your engineering work to get as much power and as much performance out of your device is just being kind of wasted by holding it back.”

Chiplets provide more of a chance for intelligent floor-planning, so that issues like stacking a logic chip on top of a logic chip can be avoided, along with the subsequent problem of trapped heat.

“You’re still integrating die very close together,” said Parry. “You’re doing it on a very high interconnect density substrate, but you’re doing it in-plane rather than stacking them. And that allows you to bring together different packages or different chiplets that have different materials. It allows you to use the most cost-optimized solution for any one of those chiplets. It also offers some opportunities for low-power designs, because through this substrate design, you can maybe take a chiplet and only ever power the parts of it that you want so you don’t end up powering bits of it that you’re not going to need. There’s literally no limit in terms of how ingenious you can be in bringing things together..”

Despite implementation challenges, the future for chiplets appears promising, especially with the development of the UCIe standard. “The chiplet idea is definitely gaining steam,” said Swinnen. “It is still a bit of a dream in the commercial space, but it’s being applied. For example, AMD has a little chiplet ecosystem inside their own company with their own products.”

As the industry moves forward with chiplets, still unresolved is a question Michael Liu, senior director of global technical marketing at JCET, posed over a year ago. “Whenever our customers talk to us about chiplets, they always ask this question: ‘How much will chiplets help us in terms of time to market?’ We always find it very challenging to quantify an answer for them. The whole value chain of heterogeneous integration is not yet clear. That’s something for all of us — OSATs, foundries and IDMs — to think about along the way.”

Related Stories
Is UCIe Really Universal?
Why developing a multi-vendor standard for plug-and-play chiplets is so difficult.

Paving The Way To Chiplets
Different interconnect standards and packaging options being readied for mass chiplet adoption.

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