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Increasing IP And SoC Debug Efficiency 10X With Intelligent Waveform Reuse


Design and verification reuse lies at the very heart of every modern chip development effort. A system on chip (SoC) project with billions of gates cannot possibly be completed in reasonable time without leveraging blocks from prior projects and commercial intellectual property (IP) offerings. These reused blocks are themselves challenging to develop since they are as large and complex as previ... » read more

Three Key Aspects Of IP Quality


It’s no secret that today’s huge system-on-chip (SoC) projects require massive amounts of design reuse. No team, no matter how talented, can design a billion or more gates from scratch. They use extensive borrowing of RTL code from previous and related projects, plus hundreds of thousands of instantiated IP blocks from internal libraries, open-source repositories, development partners, and ... » read more

Analog Design Needs To Change


It’s an exciting time to be involved in analog design! Innovation in analog design methodology has been flourishing with the introduction of new tools and improved methodologies. And this innovation is badly needed; analog design is getting tougher. Design schedules remain tight, and the technical challenges analog designers face continue to grow – especially when moving to advanced node te... » read more

How To Improve Analog Design Reuse


Digital circuit design is largely automated today, but most analog components still are designed manually. This may change soon. As analog design grows increasingly complex and error-prone, design teams and tool vendors are focusing on how to automate as much of the design of analog circuits as possible. Analog design is notoriously difficult and varied. It can include anything from power ma... » read more