Why it’s so critical to speed up analog design across a broad swath of markets, and how to get there.
Benjamin Prautsch, Fraunhofer EAS’ group manager for advanced mixed-signal automation, talks about how to simplify and speed up analog IP development, its role in IoT and IIoT/Industry 4.0, and why this is becoming so important for advanced packaging and advanced process nodes.
Companies battle it out to get artificial intelligence to the edge using various chip architectures as their weapons of choice.
Bulk CMOS, FD-SOI and finFETs all on tap as big players vie for differentiation. But where will chipmakers go after 28nm?
Experts at the Table, Part 1: Impact on the supply chain, who’s using advanced packaging, and the cost of packaging versus device scaling.
Consortiums seek ways to ensure interoperability of hardened IP as way of cutting costs, time-to-market, but it’s not going to be easy.
While CPUs continue to evolve, performance is no longer limited to a single processor type or process geometry.
Semiconductor devices face many hazards before and after manufacturing that can cause them to fail prematurely.
Interest in the open-source ISA marks a significant shift among chipmakers, but it will require continued industry support to be successful.
Slowdown due to impact on timing, and dependencies between power, thermal and timing that may not be caught by signoff tools.
Old solutions don’t necessarily work anymore, particularly at advanced nodes and ultra-low voltage.
Stacking die is garnering more attention, but design flows aren’t fully ready to support it.
Understanding aging factors within a design can help reduce the likelihood of product failures.
How Arm sees its role in emerging segments of tomorrow’s compute challenges.
New data flow, higher switch density and IP integration create issues across the design flow.
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