Analog Migration Equals Redesign

Advanced nodes are forcing design teams to make tradeoffs at each new node and with each new process.


Analog design has never been easy. Engineers can spend their entire careers focused just on phase-locked loops (PLLs), because to get them right the functionality of circuits need to be understood in depth, including how they respond across different process corners and different manufacturing processes.

In the finFET era, those challenges have only intensified for analog circuits. Reuse, for example, is a common practice in the digital world, but it hasn’t applied to analog design for quite a number of process nodes because analog circuits don’t scale beyond a certain point.

Technically, there are several reasons why this is the case. “High-precision analog designers would not feel comfortable with reuse and migration because there is no tool in analog, for example, that will guarantee timing closure,” said Mick Tegethoff, director of product marketing and management for the analog/mixed-signal verification business unit at Mentor, A Siemens Business. “We see the traditional analog designer spend a lot of time really understanding the functionality of that design.”

A growing list of physical and electrostatic effects in the finFET nodes are forcing engineering teams to take migration off the table as an option, and to reconsider the architectures and design circuitry, as well as run a lot more verification.

“Driving this are the smaller geometries that actually contain some characteristics that help analog design,” said Tegethoff. “They scale in the sense that things like leakage improve, but it doesn’t at all scale like digital. It’s not something where you just go shrink and are done. There are some things that certainly make it more difficult. For high-precision ADCs, PLLs, and precision analog circuits, as you move to smaller and smaller nodes, the random noise in the devices themselves becomes a primary factor that cannot be ignored, which needs to be accounted for in the simulation.”

For the two types of noise that are on transistors — thermal noise and flicker noise — transient noise analysis can be run within SPICE simulation. “This is a time-domain analysis, but at every time step it inserts the random noise for each of the devices,” Tegethoff said. “And while it does make stimulation take longer, design teams can simulate complex PLLs or high precision ADCs in the time domain to see it locking, see its stability.

Fig. 1: Digital vs. analog signals. Source: Wikipedia

Another growing challenge involves interconnect resistance, which is becoming a bigger problem at each new node. With interconnects, the resistance and capacitance on the interconnect itself have to be accounted for in the stimulation of the circuit. Otherwise it’s not accurate. The thinner the conductor, the greater the resistance.

“If the output of a transistor is being connected to another one, in the past you could treat that like an ideal wire with zero resistance,” he said. “Now it has some amount of resistance, which means that after the circuit is laid out, the layout parasitics must be extracted. Those must be fed back into the schematic, and simulated again with everything included. That will cause the number of elements on the circuit to go up by 100,000X, which means the simulation takes much longer. Then, if you run the simulation with the resistances and you find that it doesn’t meet the specification, then you’ve got to go back, change things, and simulate again—not to mention the additional verification this will require.

Other things driving complexity in analog IP include variability of the devices themselves, which require Monte Carlo types of analysis to make sure that the variability is a under control. Device behavior depends on layout context and surroundings, which typically falls under the heading of layout-dependent effects (LDE). Those effects have significantly increased the iterations between design and layout, said Muthu Vairavan, senior product marketing manager for design IP at Cadence.

“Further, the use of multi-patterning to print these lower geometries has increased the custom layout cycle time, owing to the complex design rules,” Vairavan said. “Analog designers also need to account for line-edge roughness-related mismatch effects and interconnect variations at these lower feature sizes. The advent of finFETs places additional constraints on analog designs, as the device widths now have to be a discrete multiple of fins (unlike a planar transistor). The devices also are susceptible to manufacturing variations in fin width and height, as well as via and interconnect resistance, which complicate analog matching.”

While analog designers and tool vendors have adapted to these changes with new design methodologies and tool flows, every node comes with new complexities resulting in cost and time-to-market challenges, Vairavan noted. “An increasing trend seen in high-performance enterprise applications is a move from a SoC to a system in package (SiP) design, where multiple analog and digital dies are integrated inside a package. This allows the digital design to move to the advanced nodes for product differentiation, but still use proven analog IP from an older node. This is driven by advances in multi-chip modules and 2.5D integration technology, and increased availability of high-bandwidth, low-power in-package interconnect.”

Still, the challenge continues to exist for low-cost system applications, where increased cost of package-level integration is not justified. “Even in high-performance datacenter and cloud applications, key mixed-signal designs like very high-speed DSP-based SerDes will benefit from the tighter densities and lower power of the advanced nodes. So the analog designers will need to continue to innovate, and the foundries and tool vendors need to incorporate analog design feedback early on in the process and tool development cycle to mitigate some of these challenges. Analog IPs are the key differentiators in many SoC designs, and their performance and quality are essential to the success of these products,” Vairavan added.

Fig. 2: Not everything can be digitized. Source: Center Point Audio

Node and foundry challenges
Process migration for analog circuitry always has been troublesome, but it has become even more of an issue in the finFET world.

“Because of the challenges with advanced nodes, the old technique of what people would call migration was somewhat synonymous with compaction, where you take an existing layout of, say, a PLL for an older node such as 350nm add a multiplier of 0.X,” explained Ed Petrus, technical advisor at ArterisIP. “For analog, that was always problematic because analog circuits are under very strict requirements for design techniques like matching, which is when there are two wires running in and out of something like a differential pair type of circuit and the current of those two wires must match. This was achieved by very strict placement of the devices in that circuit. The problem with the old style of compaction was that, because it is an algorithm, it doesn’t understand these strict requirements. In the analog world, they call them constraints. These requirements of matching end up, by the act of compaction, unknowingly breaking those requirements. Therefore the resulting circuit would simply not work.”

This has been a problem starting at 180nm. Below that everything requires a redesign.

“The device characteristics change so much that the designer has to take a fresh look at the circuit and determine whether the existing typology of the circuit can actually work for that new node,” said Petrus. “If it can work, then the topology is maintained and device sizes are tweaked, which generally may be enough. But for advanced nodes this is highly unlikely, so design teams end up revisiting the circuit and redesigning for the most part.”

Advanced process nodes simply were not created with analog characteristics in mind. They were developed to leverage area scaling of digital circuits.

“The reality is that analog circuits and analog interfaces end up being required to be integrated into digital blocks, and of course people who are designing these blocks and people who want to integrate them do face challenges, which can be addressed,” said Manuel Mota, product marketing manager at Synopsys.

These challenges stem from the intrinsic characteristics of the processes. While some of these effects started showing up even in bulk processes, with finFETs they become more pronounced, Mota said. “Also, the devices themselves are much more complex and the modeling of them becomes more complex, as well, and more difficult to use. The characteristics are no longer dependent on the immediate proximity of the intrinsic device. The proximity effects now go well beyond what were the usual effects, and designers no longer can design assuming some characteristics of the transistor. It must be assumed inside of a big circuit, and all of these effects that come from around it must be taken into account. This is true not only for the device, but also for the connectivity that goes around the devices. So when you connect one device with the other, this is also quite complex.”

Even with metal stacks it used to be that they could be considered almost ideal, but now resistances, capacitances and parasitics all play a huge role in the characteristics of the overall circuit design. Additionally, there are effects specifically related to the finFETs.

“You can no longer design with whatever gate widths and gates lengths that you want, which was possible in the past,” Mota said. “What this means for the analog design is that first, the process is typically less characterized for analog design, so there are more uncertainties as to the electrical characteristics of the circuit. The rules that you have to follow and verify against are much more complex, combined with the verification of the design that also becomes even more time-consuming, as it can be multiplied by three or four times easily in advanced nodes.”

Moreover, things that the design would not have been sensitive to in the past in very conservative electrical analog nodes, such as aging and reliability, are now critical—especially in automotive, medical and industrial applications.

“You need to design against them and verify it all,” he said. “That again extends the cycle of design. And in analog, where you’re dealing with fine evolutions of voltages and currents along the time in the simulations, this can mean very long verification cycles. This is one of the main challenges. Then, when it comes to the characteristics of the process and of the device, they are not necessarily ideal for analog design, where you have let’s say a digital-centric device with poor analog characteristics. Maybe they are poorly modeled from an analog perspective, and these are typically not addressed by modern analog design, not addressed by the traditional techniques where you want to create a linear design. In a way, you do the opposite. You accept that the process is not good. You accept that the characteristics of the process, and of the transistor that you are designing with, are not very good. And what you do is take advantage of what is good in the process, like the abundance of devices. You can have millions of gates in this process basically for free and do calibrations.”

In light of all of this, tradeoffs are a delicate balance, Tegethoff said. “If you have the knowledge about the circuit and do migrate, sometimes the circuitry has to be adjusted. There is a tradeoff between the more verification you run, the more stimulation you run, the more variability-aware simulation you run, the less margin you have to have, so something bad doesn’t happen. And unfortunately in analog, a lot of the margin is either area or power. To reduce the impact of noise, you increase power and things like that. Finally, the models of the devices themselves are more complex. FinFET device models have three or four times more equations.”

Issues for analog IP at advanced nodes boils down to everything getting more complex, and what were third-order effects becoming first-order effects. “The net result is a continuing requirement for SPICE-accurate simulation at those nodes with longer simulations, more simulations, and the need for smart environments to do things like smart Monte Carlo continues to put a demand on the circuit simulator to continue being accurate, but become faster, handle bigger circuits so that they can get their job done in a reasonable amount of time,” Tegethoff said.

Looking ahead, considering what’s needed to support the frequencies and the bandwidth of technologies like 5G and the like, an artist is still needed to figure it all out. This is extremely complex, and becoming even more so.

“Analog content is just becoming more and more important because it all lies at the boundaries,” Tegethoff observed. “It’s the edges. Whether it’s in IoT, communications, or in the car, you must deal with the analog world. Those interfaces need to be faster, they need to stay accurate, and they need to be low-power.”

And what was once a somewhat isolated art now has to deal many of the same problems as advanced digital designs, but with some unique analog twists thrown in.


Tim Regan says:

Analog process migration can be very successful and certainly works at smaller process nodes. FinFET will bring extra challenges as will moving from bulk silicon to SOI but effective migration can move a circuit far more quickly than redesign.

Our company has been providing analog migration tools and services for many years and has delivered a wide variety of products, from small precision PLLs through to wireless transceivers and SerDes. The key is to use the Process Design Kit (PDK) for both schematic and layout to ensure compliance with the target foundry’s models and device structures.

Early stage migration can also be of huge benefit when evaluating a new process. A schematic and test benches can be migrated and ready for simulation in a few hours and then tuned from there. The migration tools resolve the physical and parameter differences for the PDK elements, leaving the engineer to work at the circuit level.

Layout is much more complex but the same principles apply: migrate using parameterized cells and keep the matching and signal positions exactly as they were, making small adjustments for the constraints of new design rules. This soon gives a circuit for extracted simulation so engineers can perform accurate tests using foundry supported data.

Shrinking design cycles mean that designers must find ways to deliver their products quickly. IP vendors can’t offer their circuits in every process but migration can move them to new nodes or foundries when new licensing opportunities arise. A key to the mixed signal IP business is being able to offer tested circuits in the customer’s choice of process and migration is often the fastest and most effective way to do it.

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