Variation In Low-Power FinFET Designs


One of the biggest advantages of moving to the a leading edge process node is ultra-low voltage operation, where devices can achieve better performance using less power. But the latest generation process nodes also introduce a number of new challenges due to increased variation that can affect everything from signal integrity to manufacturing yield. While variation is generally well understo... » read more

3D NAND Flash Wars Begin


3D NAND suppliers are gearing up for a new battle amid a period of price and competitive pressures, racing each other to the next technology generations. Competition is intensifying as a new player enters the 3D NAND market—China’s Yangtze Memory Technologies Co. (YMTC). Backed by billions of dollars in funding from the Chinese government, YMTC recently introduced its first 3D NAND techn... » read more

Changing The Design Flow


Synopsys’ Michael Jackson talks with Semiconductor Engineering about why it’s becoming necessary to fuse together various pieces of digital design. https://youtu.be/AOWh4wjw-ps » read more

Embedded FPGA Timing


Namit Varma, senior director of Achronix’s India Technology Center, explains how to time an eFPGA, what can go wrong, what are the different clocking scenarios, and what impact variation has on the process. https://youtu.be/Jq4XUKnniB4 » read more

More Sigmas In Auto Chips


The journey to autonomous cars is forcing fundamental changes in the way chips are designed, tested and tracked, from the overall system functionality to the IP that goes into those systems. This includes everything from new requirements for automotive-grade chips to longer mean time between failures. But it also makes it far more challenging, time-consuming and complicated to create these d... » read more

Five DAC Keynotes


The ending of Moore's Law may be about to create a new golden age for design, especially one fueled by artificial intelligence and machine learning. But design will become task-, application- and domain-specific, and will require that we think about the lifecycle of the products in a different way. In the future, we also will have to design for augmentation of experience, not just automation... » read more

Defect Reduction At 7/5nm


Darin Collins, director of metrology at Brewer Science, talks about the cause of defects at advanced nodes and how material purity increasingly plays a role in overall quality and yield. » read more

Practical Methods To Overcome The Challenges Of 3D Logic Design


What should you do If you don’t have enough room on your floor to store all your old boxes? Luckily, we live in a 3D world, and you can start stacking them on top of each other. The Challenge: How can we shrink logic devices? Logic designers are currently facing even bigger challenges than you might be having in tidying up your storage area. Not only are logic cells highly packed together... » read more

Emulation-Driven Implementation


Tech Talk: Haroon Choudry, director of Prime Power at Synopsys, talks about how to shorten time to market and increase confidence in advanced-node designs, while also reducing the amount of guard-banding and improving design freedom. https://youtu.be/xT3CIqjnaBk » read more

Analog Migration Equals Redesign


Analog design has never been easy. Engineers can spend their entire careers focused just on phase-locked loops (PLLs), because to get them right the functionality of circuits need to be understood in depth, including how they respond across different process corners and different manufacturing processes. In the finFET era, those challenges have only intensified for analog circuits. Reuse, fo... » read more

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