Boosting Analog Reliability


Aveek Sarkar, vice president of Synopsys’ Custom Compiler Group, talks about challenges with complex design rules, rigid design methodologies, and the gap between pre-layout and post-layout simulation at finFET nodes. https://youtu.be/JRYlYJ31LLw » read more

Top Tech Talks Of 2018


2018 shaped up to be a year of transition and inflection, sometimes in the same design. There were new opportunities in automotive, continued difficulties in scaling, and an explosion in AI and machine learning everywhere. Traffic numbers on stories give a snapshot of the most current trends, but with videos those trends are even more apparent because of the time invested in watching those v... » read more

Multi-Beam Mask Writing Finally Comes Of Age


Elmar Platzgummer, chief executive of IMS Nanofabrication, sat down with Semiconductor Engineering to discuss photomask and mask writing trends. IMS, a subsidiary of Intel, is a supplier of multi-beam e-beam systems for photomask production. What follows are excerpts of that conversation. SE: For years, photomask makers have used single-beam e-beam tools to pattern or write the features on ... » read more

Variation At 10/7nm


Klaus Schuegraf, vice president of new products and solutions at PDF Solutions, explains why variability is a growing challenge at advanced nodes, why middle of line is now one of the big problem areas, and what happens when a via is misaligned due to a small process variation. https://youtu.be/jQfggOnxZJQ » read more

Thermal Impact On Reliability At 7/5nm


Haroon Chaudhri, director of RedHawk Analysis Fusion at Synopsys, talks about why thermal analysis is shifting left in the design cycle and why this is so critical at the most advanced process nodes. https://youtu.be/wjkrEFLb2vY » read more

Variation’s Long, Twisty Tail Worsens At 7/5nm


Variation is becoming a bigger challenge at each new node, but not just for obvious reasons and not always from the usual sources. Nevertheless, dealing with these issues takes additional time and resources, and it can affect the performance and reliability of those chips throughout their lifetimes. At a high level, variation historically was viewed as a mismatch between what design teams in... » read more

Variation In Low-Power FinFET Designs


One of the biggest advantages of moving to the a leading edge process node is ultra-low voltage operation, where devices can achieve better performance using less power. But the latest generation process nodes also introduce a number of new challenges due to increased variation that can affect everything from signal integrity to manufacturing yield. While variation is generally well understo... » read more

3D NAND Flash Wars Begin


3D NAND suppliers are gearing up for a new battle amid a period of price and competitive pressures, racing each other to the next technology generations. Competition is intensifying as a new player enters the 3D NAND market—China’s Yangtze Memory Technologies Co. (YMTC). Backed by billions of dollars in funding from the Chinese government, YMTC recently introduced its first 3D NAND techn... » read more

Changing The Design Flow


Synopsys’ Michael Jackson talks with Semiconductor Engineering about why it’s becoming necessary to fuse together various pieces of digital design. https://youtu.be/AOWh4wjw-ps » read more

Embedded FPGA Timing


Namit Varma, senior director of Achronix’s India Technology Center, explains how to time an eFPGA, what can go wrong, what are the different clocking scenarios, and what impact variation has on the process. https://youtu.be/Jq4XUKnniB4 » read more

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