The Rising Importance Of Design Planning

Design Planning is often overlooked in the chip design flow. The front-end designer carefully architects the design functionality to produce golden RTL. This is then poured into the synthesis engine to produce logic gates. The synthesized netlist is then thrown over the wall by the front-end designer for physical implementation.

The back-end designer receives a gate-level netlist, timing constraints, and physical constraints in the form of a floor plan. They proceed to place and route the design while fighting the competing requirements of timing, congestion, and power. SI issues, IR drop, and DRC fixing are among the final challenges that need to be overcome before tapeout.

Like a middle child, design planning often gets very little attention. The front-end team is focused on delivering an error-free, feature-rich design. The back-end team is focused on meeting timing as fast as possible with the given constraints. However, current market sector demands, and advanced process technology requirements force us to take another look at this key step.

There has been an explosion in the number of AI chip design starts in the past eighteen months. Both established companies and a growing number of startups have thrown their hat in the ring. Two important characteristics of these designs is that they are very large, and there is a lot of replicated logic. For many companies, design planning involves creating the die, planning the IO, placing the RAMs, and routing the PG network. The design quickly moves to implementation to perform a single, flat, place and route. This approach is sufficient for relatively small designs (less than three million instances). However, AI chips are pushing design sizes up into the tens of million instances. This has a devastating impact on run time, disk space, and memory.

This has forced many companies to evolve from a flat flow implementation methodology to a hierarchical one. A hierarchical approach enables a design team to employ a divide-and-conquer strategy. The key decision is how to partition the logic into smaller more manageable pieces, so they can be implemented in parallel. Choosing the wrong logic partitions can lead to loss of QoR and make the implementation more difficult. A robust design planning methodology should include connectivity analysis of the logical hierarchy to ensure high quality partitioning.

AI designs typically have a lot of replicated logic. These logic blocks can be replicated hundreds or thousands of times. A hierarchical approach allows a physical designer to carefully floor plan a single block and reuse it for each replicated instance. While it saves time floor planning each block, it also complicates the flow. Feed throughs nets, associated repeaters, and retiming registers added to any of these blocks must be replicated in all the others. The tool and the flow must handle these common changes.

IoT and mobile designs are sensitive to power consumption since they often run on battery. In fact, most chips are sensitive to power these days to avoid thermal and reliability issues. This requires a robust power planning methodology that can handle multiple voltage domains, power switches, secondary power routing, and special cell insertion. Power analysis and estimation has become a key driver in physical implementation, but it must be tightly integrated with the design planning flow to achieve the design requirements.

Although new process nodes offer improved PPA, they also add complexity to design planning. To realize the benefit of these advanced processes, and increase the yield, a precise set of rules must be obeyed by cell placement and routing. Traditionally, DRC checking is performed after place and route and then failing cells and wires are slightly adjusted to meet the requirement. However, the advanced node rules are so disruptive that they can’t easily be fixed “after” implementation. Instead, foundries are putting correct-by-construction requirements on the floor plan to ensure rules will be honored “before” implementation. These rules include boundary cell insertion, row site multiples, hard macro offsets, and PG wire and via coloring. Each foundry and each node have its own floor plan rules, so it is important to review the requirements and consider the flow impact when starting a design on a new process node.

Synopsys IC Compiler II design planner has been architected to handle these challenging scenarios. The scalable data model and unique block views efficiently support designs of 100+ million instances. Job distribution simplifies the transition from a flat flow to a hierarchical approach by reducing the overhead of setting up multiple runs. Additionally, Transparent Hierarchy gives design planning engines and tools direct access to block-level floor plans which eases the traditional burden of working with physical hierarchies. Multiple Level Physical Hierarchy and Multiply Instantiated Blocks technology handles nesting and replication of blocks respectively, which is important for AI designs.  Multi-voltage aware power planning handles complex power scenarios, special cell insertion and analysis; including native support for automatic PG fixing in IC Compiler II with RedHawk Analysis Fusion. IC Compiler II has been certified at all the leading foundries and on the latest process nodes. The design planning commands and rule checker ensure floor plans comply with advanced node rules to avoid costly floor plan iterations.

As you pack more functionality into yours designs and you move to lower process nodes, remember design planning. A well thought out flow can save you time, money and resources.