Why Shift Left?

By Michael White - 24 Aug, 2023 - Comments: 0

As every integrated circuit (IC) design company knows, the faster a design can progress from implementation to signoff verification, the better the chances are of meeting tapeout schedules. Meeting tapeout schedules improves a company’s chances of reaching their market targets. But as companies create larger and more complex ICs and move to advanced process nodes, the challenge of achieving t... » read more

Low-Power IC Design Without Compromise

By Janet Attar - 09 Mar, 2023 - Comments: 0

In the process of creating ICs, the digital implementation stage is focused on meeting the performance, power, and area (PPA) targets defined for the design. Traditionally, when talking about PPA metrics, “performance” has been the primary focus, with power and area recovered where possible, after meeting timing. But as designs have moved to smaller, more advanced process nodes, and as s... » read more

Beyond Human Reach: Meeting Design Targets Faster With AI-Driven Optimization

By James Chuang - 23 Feb, 2023 - Comments: 0

The implementation flow for semiconductor devices is all about optimizing for power, performance, area (PPA), or some combination of these attributes. The history of this flow in electronic design automation (EDA) tools is all about adding more automation, tightening iterative loops, and reducing the number of iterations. The goal is converging to the PPA targets faster while using fewer resour... » read more

Fusing Implementation And Verification

By Ed Sperling - 02 Mar, 2020 - Comments: 0

Susantha Wijesekara, senior application engineer at Synopsys, drills down into how to re-use Tcl scripts for static verification, what needs to be done with those scripts to make that possible, why that is critical to “shift left,” and how that approach saves time, money, and improves quality. » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: implementation

Why Shift Left?

Low-Power IC Design Without Compromise

Beyond Human Reach: Meeting Design Targets Faster With AI-Driven Optimization

Fusing Implementation And Verification