Beyond Human Reach: Meeting Design Targets Faster With AI-Driven Optimization

Integrating logic synthesis, place and route, and timing signoff into a single step eliminates surprises in the implementation flow.


The implementation flow for semiconductor devices is all about optimizing for power, performance, area (PPA), or some combination of these attributes. The history of this flow in electronic design automation (EDA) tools is all about adding more automation, tightening iterative loops, and reducing the number of iterations. The goal is converging to the PPA targets faster while using fewer resources.

It’s easy to sketch out a brief history. Designers used to lay out their design manually with rectangles, and then draw schematics with automated place and route. The introduction of hardware design languages (HDLs) such as Verilog enabled the use of logic synthesis tools to automate a good portion of the design phase as well as the layout.

While a major advancement in speed and efficiency, this flow still had issues due to the disconnected steps. The logic synthesis tool might do a fine job of optimizing for the specified PPA targets, but then the place-and-route tool might be unable to match the results. In many cases, an independent post-route timing signoff tool would also yield different results than predicted by logic synthesis.

These issues required the designer to go back and adjust the synthesis parameters and try again. This generally resulted in many manual iterations by the designer as well as the use of pessimistic margins to try to accommodate surprises in layout and timing signoff. The upshot was a highly inefficient flow and an end design with sub-optimal PPA attributes.

Later generations of these tools improved the situation some. Divergence could be reduced if the synthesis tool was layout-aware or able to link to a layout engine for final check before handing off to full layout. In the same vein, layout tools linked to signoff timing analysis could help close the convergence gap.

The solutions available today that employ such a flow are insufficient for large, complex designs at deep submicron technology process nodes. The implementation process remains iterative, with multiple lossy hand-offs, and still consumes too many precious human resources. Addressing this situation requires two key additional innovations: integration of all three tools into a single shell within a hyperconvergent flow and AI-driven design implementation.

Integrating logic synthesis, place and route, and timing signoff into a single step eliminates surprises in the implementation flow. If a particular design optimization is going to cause problems in layout, or if a particular net routing is going to break timing, the integrated shell “knows” this and can avoid the problem proactively. This clearly saves time and resources, but it also improves PPA results by eliminating the need for pessimistic margins.

AI technology provides benefits to all parts of the implementation flow by automatically exploring available options, leveraging project history, and autonomously converging to PPA targets with minimal human effort.

Synopsys provides an AI-driven design implementation solution using its Design Space Optimization AI ( technology and Synopsys Fusion Compiler RTL-to-GDSII implementation system. The unique single shell implementation flow ensures that the AI-driven optimization can rely on a convergent RTL-to-GDSII flow providing consistent and reliable feedback to efficiently explore trillions of possibilities without needing to manage the various handoffs and discrepancies between multiple tools.

The key to improvements by AI-driven exploration lies in the nature of design optimization, which relies on heuristics. There is no one heuristic, or even a set of heuristics, that is best for every design. EDA vendors choose the heuristics that provide the best overall results across all designs. There are typically several dozen more options hidden within each tool for experienced Field Application Engineers to leverage for specific designs, but users exploring these options manually is not feasible due to time, resource, and expertise limitations.

This is especially true for logic synthesis. The degrees of freedom available during the layout phase are relatively limited since gates and their interconnection have already been fixed. During synthesis, AI-driven optimization can make architectural-level decisions that can improve PPA results by double digits.

Enabling AI-driven optimization during synthesis has significant efficiency advantages as well. Thanks to the RTL-to-GDSII full flow enablement of AI, the learnings from one design step can be seamlessly and effectively leveraged by all subsequent design steps, tightening the design space to be optimized, and can result in accelerated time-to-results while using fewer compute resources. Based on a recent case study, an AI-driven route optimization step can use up to 10X less computing while achieving the same PPA and time-to-results targets when a learning database from the logic synthesis stage is available.

The learnings are also saved so that this knowledge can be used in subsequent runs for a derivative or highly relevant design, improving the efficacy and efficiency of AI-driven optimization. This unlocks PPA optimization opportunities never reachable by human exploration, regardless of time, and designers do not have to keep track of which settings worked best.

While learning databases cannot be easily shared across different companies, AI configurations and human experiences with AI can. Accumulated through various types of AI-driven optimization exercises, provides a collection of SpaceWare Applications (Apps) to perform common optimizations such as flow, library, power, floorplanning, and voltage with out-of-the-box success. Customer presentations at wordwide SNUG events have documented these Apps delivering up to 15% less area, 20% reduction in power consumption, and 25% faster operating frequency across a wide range of design styles and process nodes.

The unique combination of integrated tools in a hyperconvergent flow and deployment of AI technologies in both logic synthesis and layout provides the solution needed for implementation of today’s most advanced chip designs. This is an area of rapid innovation, with more customer results being reported every day. For all the latest information on meeting PPA targets with AI-driven optimization, please attend the Lunch Panel “How AI Is Driving the Next Innovation Wave for EDA” and the related tracks at SNUG Silicon Valley 2023. Detailed information is available can be found here.

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