tag: DRC

Mastering 3D-IC Verification Complexity
By Matt Grange - 11 Jun, 2026 - Comments: 0

The semiconductor industry's transition from traditional 2D integrated circuits to 2.5D and 3D-IC configurations represents more than an incremental advancement. This architectural shift, driven by the need to push beyond conventional scaling limitations, introduces a cascade of verification challenges that legacy methodologies struggle to address. As designs incorporate multiple stacked dies, ... » read more

A Comprehensive Approach To 3D-IC Physical Verification
By Siemens EDA - 05 Jun, 2026 - Comments: 0

3D integrated circuits (3D ICs) are reshaping semiconductor development. While these architectures deliver significant performance, power and integration gains, they introduce new challenges in verification—across electrical, thermal and mechanical domains. Siemens Calibre offers a comprehensive platform for 3D IC physical verification, linking DRC, LVS, advanced thermal simulation, mechanica... » read more

From Billions Of Violations To Actionable Insights: Calibre Vision AI
By Siemens EDA - 29 May, 2026 - Comments: 0

As advanced node SoCs increase in size and complexity, early full-chip DRC runs frequently produce hundreds of millions to billions of violations. This overwhelming scale leads to new challenges—not just in running checks, but in comprehending results, setting priorities, and coordinating closure across teams. Introduced in 2025, Calibre Vision AI enabled instance-complete, AI-guided triage a... » read more

Automating Traditional PCB Layout Verification With Electrically Based Design Rule Checks
By Rory Riggs - 28 May, 2026 - Comments: 0

Electrical verification and sign-off of a printed circuit board (PCB) is a challenging, tedious, and manual process. If time permits, this visual inspection to catch errors that might cause costly respins is done throughout the PCB layout process, but traditionally it is performed only once at the end of the design cycle. This approach creates significant project delays when issues are discover... » read more

Transforming DRC Closure At Advanced Nodes
By James Paris - 30 Apr, 2026 - Comments: 0

If you’re working on SoCs at 2 nm or below, you know DRC is a different beast these days. Early in the design, it’s common for DRC runs to dump hundreds of millions—or even billions—of violations at your feet. And that’s when everything is changing fast: block interfaces aren’t fixed and constraints are shifting with every new iteration. Making sense of these massive result sets, fi... » read more

The Power Of Shift-Left DRC Verification With Calibre nmDRC Recon
By Siemens EDA - 23 Dec, 2025 - Comments: 0

As integrated circuit (IC) designs grow in complexity, traditional design rule checking (DRC) methods struggle to keep pace. Originally developed for simpler, custom layouts, traditional DRC uses an iterative “construct by correction” method. However, with the rise of automation and multi-layered design hierarchies, relying on traditional sequential DRC approaches can create substantial run... » read more

Managing Complexity: Evolving Approaches To Design Rule Checking In Modern IC Design
By John Ferguson - 23 Dec, 2025 - Comments: 0

As integrated circuit (IC) designs have grown in complexity, scale and speed requirements, design rule checking (DRC) has evolved from a routine step into a critical pillar of successful tapeouts. Foundry rules, shrinking geometries and advanced patterning have increased both the engineering effort and computational overhead needed for verification. Today, DRC isn’t just about sign-off—it... » read more

Securing IP Integrity In Advanced SoC Design
By Sara Khalaf - 25 Nov, 2025 - Comments: 0

In today’s complex system-on-chip (SoC) design flows, intellectual property (IP) blocks are everywhere—licensed from third parties, leveraged from internal libraries, or hand-crafted by expert teams. These IPs are typically delivered in a “black box” format and are expected to remain unchanged throughout the physical design stages, from initial floorplanning to top-level placement, rout... » read more

How To Transform Verification Time-To-Results
By Priyank Jain - 28 Aug, 2025 - Comments: 0

The clock is ticking. Your team has just completed another full-chip DRC run on a complex 5nm SoC, and the results are overwhelming: millions of violations across hundreds of blocks. With tape-out deadlines approaching, you need to quickly identify which issues are critical, which are systematic and which blocks require immediate attention. Every day spent in DRC debug is a day delayed to marke... » read more

Rethinking Chip Debug
By Priyank Jain - 30 Jun, 2025 - Comments: 0

By Priyank Jain and James Paris The semiconductor industry has spent decades mastering the art of integrated circuit physical verification. But as system-on-chip (SoC) designs push the boundaries of complexity—with more transistors, greater integration and larger silicon areas—the established debug strategies are breaking under the weight of scale. Today’s advanced chips can generate a... » read more

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