Automating Traditional PCB Layout Verification With Electrically Based Design Rule Checks

Electrical verification and sign-off of a printed circuit board (PCB) is a challenging, tedious, and manual process. If time permits, this visual inspection to catch errors that might cause costly respins is done throughout the PCB layout process, but traditionally it is performed only once at the end of the design cycle. This approach creates significant project delays when issues are discovered late, as designers must redo component placement or trace routing, triggering additional sign-off cycles that can cascade over multiple iterations.

An automated rule verification process implemented throughout the PCB layout design cycle offers a better method, going beyond traditional spacing and distance checks to incorporate signal integrity (SI), power integrity (PI), electromagnetic interference (EMI), and high voltage safety rules. These rules include built-in electrical parameters, 2D field solvers, vendor-specific IBIS models, and electrical rules of thumb. By enabling designers to run these sophisticated electrical rules early and often at every stage of PCB layout, including custom rules for proprietary technologies, this automated check-and-correct approach ensures electrical protocols are adhered to while giving hardware engineers greater confidence in their placement and routing decisions throughout the dynamic design process.

Hardware designer challenges

Hardware engineers face many design challenges as PCB complexity and density have evolved dramatically over the past two decades. Numerous standards — including universal serial bus (USB), peripheral component interconnect express (PCIe), double-data rate (DDR), and high-definition multimedia interface (HDMI), among others — have become universally adopted protocols. These standards themselves are becoming increasingly complex with each generation. DDR memory, for instance, has progressed from its 1998 introduction to the upcoming DDR6 (expected in 2027), with each iteration maintained by the Joint Electron Device Engineering Council (JEDEC) standards.

Hardware designers must not only learn and understand these evolving protocols and architectures but also acquire the expertise to verify them — often having to rely on specialized experts for final electrical sign-off due to resource and time constraints. While experts previously could rely on core power and signal integrity principles to diagnose layout issues, the increasing complexity of each protocol generation has forced engineers to become highly specialized in single technologies—one person becoming a DDR expert while another focuses on SerDes, for example. This specialization means that as electrical engineering work becomes more difficult, it’s critical to focus expert efforts on deeper simulation problems that could cause or prevent board respins, as relying on these specialists for the increasingly complex PCB verification sign-off process creates a significant bottleneck in the design release timeline.

Time trade-offs for electrical verification

Where are signal, EMI, and power integrity experts spending their time in PCB verification? Most likely, the bulk of their time is spent acquiring and setting up models they’ll need to validate their design. Models can come in many forms, ranging from datasheet descriptions to complex S-parameters or 3D meshed structures. Since acquiring or generating these models themselves can be a lengthy and difficult task, it is important that the tool itself is not too complex to learn and use effectively. Ideally, tool complexity should maintain a high ease-of-use, regardless of the modeling complexity, as shown in Figure 1 below.

Fig. 1: Tool and modeling complexity.

The tools used for validation are often uniquely focused on one problem. With a free marketplace and many simulators to choose from, the best tools to solve each individual problem rise to the top. This results in the expert having a plethora of tools to choose from, but they are most likely from different vendors and thus are not integrated well. PCB verification specialists will have to invest more time to learn multiple tools and often stitch the results together by hand.

Fig. 2: Incomplete, disparate tool flows.

A major goal should be to automate tedious tasks and take easy problems off the table, allowing engineers to spend time modeling areas of the board that require it. The idea of shifting-left a portion of the simulation, to either the layout group itself or earlier in the design process, can add efficiency to the electrical sign-off process.

Manual versus automated inspection

What does PCB electrical verification entail? Traditionally, manual inspection of a PCB is a lengthy and often tedious, visual process. The expert reviewer will go layer by layer and net by net over their PCB, checking for the things that they are able to review with their current electrical engineering knowledge. As PCBs become denser and technology becomes more complex, more tradeoffs will have to be made as time is limited. Most likely, the electrical sign-off process will be an ever-growing list of items that the team must check. For example, if the layout team encounters a board re-spin, they will incorporate a design check to prevent it from happening again in the future.

Critical nets with outlying cases will also be simulated. The idea here is that if you don’t have time to simulate every net in the design, or even every net in an interface, the reviewer will check for the longest net, shortest net, and any interesting corner case. The hope is that performing a wide range of checks will likely catch issues before releasing the PCB, ensuring the design will work correctly. However, this is never a guarantee. If a review team or an expert doing electrical verification has time to inspect only some of the critical nets in a design, then it is safe to assume that they also have limited time to run visual inspections. Due to the iterative nature of the PCB layout design process, experts will save their review for the end of the design cycle, just before the board is sent to manufacturing.

Even if the skills of the engineer are sound, humans make mistakes. If you allow for only a single, final sign-off at the end of your PCB design cycle, you’re leaving a lot to chance. We’ve already established the experts’ time is sacred, and there are typically a limited number of available specialists. Automated DRC checks can run verification not just at the end but throughout the PCB design cycle. Stages of layout can be verified on demand, with quick automated checks.

Table 1: Difference between manual and automated inspection of PC.

Automated electrical rule examples

Boards that have respins caused by an EMI issue are virtually impossible to detect with simulation. Sometimes, these issues are found in the field due to unintentional radiation produced by inductance loops (breaks in return current), isolated metal, or high-speed nets at the plane edge with no shielding.

Fig. 3: Net near plane edge EMI violation.

Some issues that are found manually by visual inspection of the board, layer by layer, or net by net may be easily detected with HyperLynx DRC, an electrical rule-based PCB layout verification tool from Siemens EDA.

For example, a typical time for visually inspecting an eight-layer board to detect isolated copper could take 30 minutes to an hour shown (see Figures 4–6). HyperLynx DRC found the isolated copper and 27 other potentially harmful instances in a matter of seconds.

Fig. 4: Elapsed time for metal island check.

Fig. 5: Metal island dimmed.

Fig. 6: Metal island undimmed.

The vertical reference plane change rule is a perfect example of where electrical rule checks go beyond the traditional spacing and distance checks already found in layout tools. As a signal transitions through a via to another layer on the board, the reference plane will change for the current return path. This rule will check for a continuous return path for layer changes and reduce the risk of common-mode radiation. The parameters explicitly check for decoupling distance to nearby capacitors or stitching vias from the reference plane as it changes. It has default values for propagation delay from a stack-up or will utilize the true PCB stack-up if available. This is one rule that also has the ability to incorporate an IBIS model to use the edge rate and voltage information for more accurate rule checking, which is not supported in conventional layout DRCs.

Fig. 7: Vertical reference plane change rule overview.

Figure 7 shows an example of what a violation of the vertical reference plane change rule would look like. It highlights a circle to the specified radius of the distance set in the parameters. In this case, there’s no stitching component to ground as the reference changes from layer 17 to layer 13 on the board. The rule even gives advice on how to correct it in layout.

Fig. 8: Vertical reference plane change violation.

For reference, this rule took 59 seconds to find this violation and other potentially similar EMI issues. A traditional visual inspection of the PCB would not be able to detect such a violation. Simulation with a field solver may be necessary to see the true effect on the signal and if it is a problem that could cause a board respin.

An automated electrical rule can quickly and easily detect these potential issues, to be fixed in layout or sent off to a modeling expert to do a deeper simulation dive. By automating the detection and reducing the violation count significantly, the visual inspection process is sped up. Another byproduct is we can now focus the efforts of the SI/PI/EMI expert to model what needs to be modeled with advanced simulation software.

One of the most commonly adopted HyperLynx DRCs is the nets crossing gaps check. Traces that cross over split planes is a common visual check performed in PCB design review. If a signal that crosses over a gap in a split plane sees a change in impedance, that impedance change will cause a reflection of the signal. The speed of the signal, gap size, nearby stitching capacitor, or stitching via, and the reference plane for continuous return current, all play a role in the quality of the signal in this scenario. The nets crossing gap rule encompasses all of these checks and is shown in Figure 9.

Fig. 9: Nets crossing gaps rule overview.

Visually checking for nets crossing gaps on a design is doable but extremely tedious. This rule has immediate value to any engineer doing the PCB layout verification sign-off. At best, visually we can verify if the critical signal does indeed cross over a gap, but we cannot visually measure the impact of the signal reflection and check for nearby stitching components that have the proper ability to ground the signal. The tool accounts for these parameters as designed and points out these issues in a matter of seconds, completely replacing and enhancing the visual inspection process.

Power integrity rules

Ensuring proper power delivery is a key piece of simulating and verifying PCBs. The PI out of the box rules are an important first step in a larger PI simulation process.

Fig. 10: Out of the box power integrity rules.

Where necessary, some rules utilize spacing and distance constraints, like traditional layout DRCs. The decoupling capacitor coverage and placement rules incorporate a minimum distance check from the IC power pin to a decoupling capacitor to ensure that the components are close enough to be effective at decoupling. A key difference is that the electrical rule can use the routed length and include ground nets in the analysis.

Fig. 11: Decoupling capacitor placement and coverage rules.

This rule is equally effective at catching potential decoupling holes. If a decoupling capacitor is too far away from a power pin or the plane it’s meant to associate with, the whole design could be failing AC analysis.

Consider the scenario where a third-party verification team is hired to sign-off on a PCB layout headed to manufacturing. Running automated rules that check spacing and distance, and bring an electrical perspective, can validate the layout tool’s own spacing and distance DRCs. There is peace of mind in ensuring from another source that no mistakes were made in layout, even inadvertently.

Conclusion

PCB verification and sign-off is a multi-step process. Traditional visual inspection of a PCB can take hours or days to complete and is a tedious process that is limited by the time and expertise of the reviewer.

Automated, electrically focused DRCs incorporated into the layout tool can significantly speed the layout design process. Using rules that are easy to run and that apply SI, PI, and EMI/EMC theory allows layout experts to check and correct throughout the design flow and gives them time to make adjustments while they run the rules.

HyperLynx DRC from Siemens EDA is a PCB layout verification tool that, out-of-the-box, uses 100-plus electrical rule-based checks that span SI, PI, EMI/EMC, and high voltage safety checks. HyperLynx DRC also has its own script writing and debugging environment to support custom rule checks.

Interested in more information on this topic? There’s much more in the new Siemens whitepaper, Automating PCB electrical sign-off with rule-based verification in HyperLynx DRC.