HW methods to throttle AI; M3D DRAM; interconnect signal-integrity analysis; 3D mask effects in high/hyper-NA EUV litho; compute-in-interconnect and memory; NbAs nanowire interconnects; and 3D conformal thin-film patterning.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Hardware Mechanisms to Dynamically Throttle AI Performance | Princeton University |
| Optimization of 3D-DRAM Architecture with Oxide-Semiconductor Channel through Process and Device Simulation | imec, KU Leuven, Samsung Electronics, Lam Research |
| Fast Interconnect Signal Integrity Analysis For Integrated Circuit Design Via Graph Transformers | University at Buffalo, University of Stuttgart, IBM Research |
| Benefits of 3D mask effects in high-NA and hyper-NA EUV lithography | Fraunhofer IISB, ASML |
| Compute-in-Interconnect and Memory with Reconfigurable Precision for LLM Inference | National University of Singapore |
| Surface-dominant transport in Weyl semimetal NbAs nanowires for next-generation interconnects | Cornell University, NYCU, IBM Research, Johns Hopkins University, Penn State et al. |
| Lithographic patterning of conformal thin films on 3D structures using Scaffold-architected Lift-off masks | KTH Royal Institute of Technology |
Find more semiconductor research papers here.
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