tag: chiplets

From Data Accumulation To Data Activation: AI-Driven Data Feed Forward For Chiplet-Based Test
By Greg Prewitt - 07 Jul, 2026 - Comments: 0

For most of the industry's history, the lever for semiconductor performance gains was process-node scaling. That is no longer the whole story. As one recent industry analysis put it, advanced packaging has now displaced node scaling as the primary lever for performance gains. The consequence reaches well beyond design and assembly; it lands squarely on test. In a monolithic world, test optim... » read more

When The Test Cell Lies
By Gregory Haley - 07 Jul, 2026 - Comments: 0

Key Takeaways:   A marginal test result can be electrically valid and still diagnostically misleading because the socket, load board, and thermal loop are now part of the measurement.   Separating device drift from test-cell drift depends on tracking margins, variance, and calibration trends rather than bins alone.   In advanced packages, a false pass destroys value downstream, ... » read more

Realizing The Future Of 3D-IC Design
By Keith Felton - 25 Jun, 2026 - Comments: 0

The integration of heterogeneous chiplet technology has fundamentally transformed semiconductor design, enabling the efficient creation of sophisticated system-in-packages by assembling pre-designed or third-party IP onto high-performance interposers and advanced packages. This approach offers significant advantages over traditional monolithic designs, including enhanced performance, improved p... » read more

Wafer-Scale vs. Chiplets: The New War? Part 2
By Nandan Nayampally - 25 Jun, 2026 - Comments: 0

In Part 1, we looked at the innovations underpinning the Cerebras WSE-3 and why its most significant breakthrough is the elimination of data movement overhead at the architectural level, not better yield management or thermal engineering. Cerebras’ on-wafer fabric is a viable answer to the question being asked by the entire industry: how do you move data fast enough that compute stops wait... » read more

How Far Left Can You Shift?
By Ed Sperling - 24 Jun, 2026 - Comments: 0

More steps in the design flow are shifting left, which makes a complicated design process even more complex. This includes early software prototyping, workload mapping, verification, multi-physics integration, verification, IP qualification. Frank Schirrmeister, executive director of strategic programs for System Solutions at Synopsys, talks about the increasing number of steps, the potential t... » read more

UCIe vs. BoW: Practical Insights For Choosing The Right Chiplet Standards
By Keysight - 24 Jun, 2026 - Comments: 0

As chiplet-based architectures gain traction across high-performance and cost-sensitive semiconductor applications, selecting the appropriate die-to-die interconnect standard has become a critical design decision. This white paper presents a practical, engineering-focused comparison of Universal Chiplet Interconnect Express (UCIe) and Bunch of Wires (BoW), highlighting their differing philosoph... » read more

How To Build Billions of Bumps
By Bryon Moyer - 18 Jun, 2026 - Comments: 0

Key Takeaways: Hybrid bonding can result in a package containing billions (and eventually trillions) of connections. Building that many connections successfully requires extreme process uniformity across a wafer. Inspection isn’t practical, and test benefits from internal test mechanisms. Hybrid bonding allows unprecedented signal pitch, but fully populating dies and inter... » read more

Co-Packaged Optics Testing Faces Steep Data Center Ramp
By Anne Meixner - 09 Jun, 2026 - Comments: 0

Key Takeaways: Device interface board must balance flexibility in handling with customization for different optical connectors. Test fixtures should account for DUT socketing challenges, such as warpage, coupling, and interference. Advanced data management practices will help speed yield learning. Integrating photonic and electrical ICs into co-packaged optics (CPO) requires... » read more

The Evolution Of UCIe
By Ed Sperling - 02 Jun, 2026 - Comments: 0

Since it was released in March 2022, the Universal Chiplet Interconnect Express (UCIe) has grown from a basic way of connecting two dies together into a comprehensive specification that can ensure the handoff of data between various components in an advanced package, as well as validate the chiplets within that package. Mayank Bhatnagar, director of product marketing at Cadence, talks about the... » read more

Swapping Out Chiplets: I/Os Vs. Compute
By Liz Allan - 28 May, 2026 - Comments: 0

Key Takeaways: Companies can save time and money by swapping out a compute, memory, or I/O chiplet to gain technology improvements, while keeping the other dies stable. Chip architects may choose to keep their I/Os stable and swap out compute to move from a 5nm process node to 3nm to achieve performance and power improvements, or swap out memory from LPDDR5X to LPDDR6. Swapping out... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy