tag: chiplets

The Evolution Of UCIe
By Ed Sperling - 02 Jun, 2026 - Comments: 0

Since it was released in March 2022, the Universal Chiplet Interconnect Express (UCIe) has grown from a basic way of connecting two dies together into a comprehensive specification that can ensure the handoff of data between various components in an advanced package, as well as validate the chiplets within that package. Mayank Bhatnagar, director of product marketing at Cadence, talks about the... » read more

Swapping Out Chiplets: I/Os Vs. Compute
By Liz Allan - 28 May, 2026 - Comments: 0

Key Takeaways: Companies can save time and money by swapping out a compute, memory, or I/O chiplet to gain technology improvements, while keeping the other dies stable. Chip architects may choose to keep their I/Os stable and swap out compute to move from a 5nm process node to 3nm to achieve performance and power improvements, or swap out memory from LPDDR5X to LPDDR6. Swapping out... » read more

Wafer-Scale vs. Chiplets: The New War? Part 1
By Nandan Nayampally - 28 May, 2026 - Comments: 0

Cerebras’ IPO is a meaningful moment for the semiconductor industry — and not just for the financial implications. Their confidence in their opening price reflects something the industry has effectively acknowledged: incremental chip scaling can no longer keep pace with what AI infrastructure demands. Radical approaches are earning serious consideration and serious capital. Cerebras... » read more

Side-Channel Risks Across 2.5D/3D Integration and Chiplet-Based Systems (Grenoble INP – UGA et al.)
By Technical Paper Link - 25 May, 2026 - Comments: 0

Researchers from Grenoble INP - UGA, CNRS, TIMA have released “Spying Across Chiplets: Side-Channel Attacks in 2.5/3D Integrated Systems”. Abstract “Advanced packaging and chiplet-based integration are increasingly adopted to build complex heterogeneous systems beyond the limits of monolithic scaling. While these architectures offer major benefits in terms of modularity, yield, a... » read more

With Chiplets, What Role Does Economics Play?
By Bryon Moyer - 21 May, 2026 - Comments: 1

Key Takeaways: For the data center, chiplet economics matter, but they’re not a primary decision-driver. With the exception of processor families, chiplets cannot address consumer markets today, where economics dominate. If a chiplet marketplace materializes, the economics may be friendlier because chiplets will have multiple customers and applications. Chiplets are notori... » read more

Confusion Grows With More Interconnect Options And Tradeoffs
By Liz Allan - 18 May, 2026 - Comments: 0

Key Takeaways: Designers are frequently evaluating 5 or more different interconnects in a single system, each with a distinct purpose. While chip-to-chip (PCIe) and die-to-die (UCIe, BoW) technologies seem to be solving a similar problem, in practice they bring different challenges. PCIe, CXL, NVLink, and UALink are all active in the hyperscaler space, but Ethernet-based technologies... » read more

Smart Test Collides With The Data Chain
By Gregory Haley - 12 May, 2026 - Comments: 0

Key Takeaways: The promise of smart test is a data-chain problem before it is an algorithm problem. A device can pass every checkpoint and still carry a latent defect the test record never captured. As test grows more adaptive, the validity of the measurement environment matters as much as the measurement itself. For years, the test roadmap has pointed toward more adaptive f... » read more

Securing Chiplet-Based Platforms: Distributed Trust With Centralized Authority
By Berardino Carnevale - 07 May, 2026 - Comments: 0

In previous blogs, From Monolithic SoCs to Chiplets: A New Hardware Security Paradigm, and Developing a Security Framework for Chiplet-based Systems, we discussed why chiplets change the game from a security perspective, and why security must be addressed at a platform-level in a chiplet-based system. In a monolithic device, trust is often implicitly bounded by the die itself: sensitive asse... » read more

How To Streamline Your Advanced Package Interconnect Designs
By Maria Castillo - 30 Apr, 2026 - Comments: 0

Monolithic system-on-chip (SoC) designs was once a popular choice. However, they face significant constraints in the era of AI. By forcing all chip functions into a single die and process node, they reduce engineering, manufacturing, and design cost flexibility. In contrast, the multi-die nature of chiplets enables different SoC functions to be designed and verified independently and fabrica... » read more

From Standards To Systems: The Chiplet Era On Arm
By Nandan Nayampally - 30 Apr, 2026 - Comments: 0

For three decades, Arm didn’t just participate in industry transformation — it redefined it. From mobile to cloud to automotive, Arm’s architecture and the AMBA ecosystem have become the backbone of scalable compute. Now the industry faces its next structural shift: The era of monolithic SoCs is tapering and giving way to the era of chiplet systems. While complex SoCs are going to b... » read more

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