tag: chiplets

Rethinking ESD Protection for System-On-Integrated Chiplets (UC Riverside)
By Technical Paper Link - 28 Apr, 2026 - Comments: 0

A new technical paper, "In-SoIC ESD Protection for Chiplet-Based 3D Microsystems: Future Research Directions," was published by researchers at the University of California, Riverside. Abstract "Heterogeneous integration opens a pathway to three-dimensional chiplet-based microsystem chips. Electrostatic discharge reliability is a major challenge to future smart chips featuring rich functio... » read more

Mapping and Routing Fault-Tolerant Quantum Circuits Onto Chiplet Architectures (TU Munich)
By Technical Paper Link - 28 Apr, 2026 - Comments: 0

A new technical paper, "Chipmunq: A Fault-Tolerant Compiler for Chiplet Quantum Architectures," was published by researchers at the Technical University of Munich. Abstract "As quantum computing advances toward fault-tolerance through quantum error correction, modular chiplet architectures have emerged to provide the massive qubit counts required while overcoming fabrication limits of mon... » read more

When Semiconductor Materials Misbehave
By Gregory Haley - 27 Apr, 2026 - Comments: 0

Key Takeaways Material behavior in production depends on the process context that no development environment can fully replicate. In advanced packaging, the interactions that cross domain boundaries are increasingly where failures originate. The most accurate materials data is also the most commercially sensitive, leaving simulation models calibrated against generic inputs rather tha... » read more

System-in-Package Challenges
By Ed Sperling - 23 Apr, 2026 - Comments: 0

Systems companies and leading-edge chipmakers are pushing past reticle limits with chiplet-based designs, often breaking compute-intensive functions into different chiplets and coupling those with other chiplets that may have been developed by different teams and at different process nodes. This is harder than it sounds, and results can vary widely even under the best circumstances. Nir Sever, ... » read more

Panel-Level Packaging’s Second Wave Meets Engineering Reality
By Gregory Haley - 16 Apr, 2026 - Comments: 0

Key Takeaways Panel-level packaging is arriving not because the engineering is ready, but because wafer-level economics are breaking down. Glass improves the warpage and dimensional stability problems of organic substrates but introduces a different class of failure modes that require materials solutions, not process adjustments. The central challenges of panel-level processing are m... » read more

Chiplet Standards Aim For Plug-n-Play
By Bryon Moyer - 16 Apr, 2026 - Comments: 0

Key Takeaways Die-to-die chiplet standards are only the beginning. Many more standards are necessary for a chiplet marketplace. A number of such standards have either had initial versions released or are in progress. Existing work covers packaging, a system architecture, various design kits, a universal link layer, and updates to BoW. Today’s chiplets exist in silos. In a ... » read more

Breakthrough Thin GaN Chiplet Technology
By Han Wui Then - 16 Apr, 2026 - Comments: 0

Researchers at Intel Foundry have demonstrated a gallium nitride (GaN) chiplet technology built on 300 mm GaN-on-silicon wafers, marking a significant leap forward in semiconductor design. Presented at the 2025 IEEE International Electron Devices Meeting (IEDM), this work tackles one of the most pressing challenges in modern computing: how to deliver more power, speed, and efficiency in an incr... » read more

Why More CPUs Are Needed For Agentic AI
By Ed Sperling - 15 Apr, 2026 - Comments: 0

The shift from generative AI to agentic AI will significantly increase the amount of compute power needed in data centers. Queries to search for and analyze data from multiple sources will be performed simultaneously by agents and without human intervention, rather than a single request from a live person. Jeff Defilippi, senior director of product management at Arm, talks about the impact of r... » read more

Developing A Security Framework For Chiplet-Based Systems
By Berardino Carnevale - 02 Apr, 2026 - Comments: 0

In a previous blog, From Monolithic SoCs to Chiplets: A New Hardware Security Paradigm, we discussed why chiplets change the game from a security perspective, and why security must be addressed at a platform-level in a chiplet-based system. In a monolithic SoC, device identity is often anchored in a single root of trust that owns key material and policy. In a chiplet platform, every security... » read more

Preparing For The Multiphysics Future of 3D ICs
By Siemens EDA - 01 Apr, 2026 - Comments: 0

3D integrated circuits (3D ICs) are emerging as a revolutionary approach to design, manufacturing and packaging in the semiconductor industry. Offering significant advantages in size, performance, power efficiency and cost, 3D ICs are poised to transform the landscape of electronic devices. However, with 3D ICs come new design and verification challenges that must be addressed to ensure success... » read more

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