How To Streamline Your Advanced Package Interconnect Designs

Monolithic system-on-chip (SoC) designs was once a popular choice. However, they face significant constraints in the era of AI. By forcing all chip functions into a single die and process node, they reduce engineering, manufacturing, and design cost flexibility.

In contrast, the multi-die nature of chiplets enables different SoC functions to be designed and verified independently and fabricated on a cost-effective process node.

What are the market drivers behind chiplets?

Figure 1. Monolithic vs. chiplet-based chip designs.

Compared to monolithic SoCs, chiplet-based SoCs confer several benefits:

• better energy efficiency and lower power consumption,eg. pJ/bit
• more cost-effective using mix-and-match process node
• better thermal performance
• higher fabrication yields
• heterogeneous multi-vendor integration through open standards like the universal chiplet interconnect express (UCIe) and bunch of wires (BoW)
• faster development time

Figure 2. Multi-die chiplets from different vendors.

As a result, the chiplet ecosystem is rapidly expanding in crucial domains like:

• artificial intelligence (AI)
• high-performance computing (HPC)
• data centers
• networking (gigabit and optical)
• automotive
• radio frequency applications (like 5G and 6G)

At the same time, the complexity of chiplet connectivity is also scaling quickly, starting from 2D, and 2.5D/3D stacked advanced packages. These packaging technologies rely on silicon interposers, silicon bridges, and organic substrates that create various design challenges and associated product-to-market risks.

What are the late-stage signal integrity risks of chiplet interconnects?

Figure 3. Eye diagrams of a lossy channel (black) and a lossless channel (yellow), with rise time degradation shown by the red dotted line.

The unique characteristics of chiplets and the advanced packaging create significant concerns for signal integrity (SI) and power integrity (PI) engineers, for example, unconventional ground return path using hatched ground planes instead solid ground planes.

Late-stage discovery of SI/PI issues can be catastrophic, leading to costly design respins. Early-stage prevention is ideal, but unfortunately, existing EDA workflows often lack the tools to do so effectively.

Key concerns are outlined below:

• Ground/return path risks: Hatched (waffled) ground planes in the silicon bridges and interposers can disrupt signal return paths. Unfortunately, they are necessary due to silicon manufacturing constraints; however, they are very difficult to model. If not modeled correctly, they can lead to SI failures, such as closed eye, compliance issues, and non-optimum performance.
• Crosstalk: As interconnects become denser (e.g., in 2.5D and 3D stacking) and with the increased use of hatched ground planes, crosstalk could increase.
• Reflections go up due to impedance mismatches due to non-uniform hatched ground planes.
• Strict standards: Interconnect standards like UCIe and BoW have rigorous electrical requirements to ensure interoperability. SI engineers adhere to 1) correct voltage transfer functions (VTF) to ensure that insertion loss and crosstalk meet the requirements for given data rates and packaging types, 2) eye margin standards at the receivers to enable error-free transmissions, and 3) well-behaved forwarded clocking including QDR.
• Probing difficulties: It’s nearly impossible to physically probe these dense interconnects with very small pitch size at the u-bump level. Engineers must rely entirely on simulations and virtual probes.
• Heterogeneous integration risks: Since chiplets often come from multiple vendors, interoperability becomes complicated. Engineers must verify that the cumulative effects of different materials, process nodes, and signaling protocols work seamlessly . Ensuring stable power delivery across chiplets without voltage drops or resonances is critical.

What concerns high-speed digital designers about chiplet interconnects?

Figure 4. Simplified chiplet package view with die-to-die PHY interfaces (orange traces)

Apart from the SI concerns above, high-speed digital design engineers also worry over the following aspects of chiplet interconnects:

• Package modeling difficulties: Accurate modeling is lacking for stacked interconnects, high-speed digital wide buses with hatched grounds (such as UCIe 2.5D/3D packages), Through silicon vias (TSVs), and hybrid bonding. These approaches are used in high-bandwidth memory and graphical processing units (GPUs), which are critical to AI data centers.
• Higher loss in Silicon: High-speed interconnects attenuate high-frequency components more than low-frequency ones, leading to rise-time degradation and intersymbol interference (ISI). The resulting slopes and closure in the eye diagram reduce the timing and voltage margins for reliable transmission. This can be amplified in lossy silicon materials.
• Die-to-die (D2D) communication testing: Standardized interfaces between chiplets from different vendors are difficult. Engineers must verify interoperability without being able to probe inside the finished package. Virtual prototyping and simulations are the only viable verification methods.

What worries architects and managers about chiplet interconnect designs?

The early-stage blind spots in chiplet interconnect decisions worry various other stakeholders in the semiconductor industry. Modern multi-die systems have to decide a good system partitioning, choose the right package technology, for example silicon or organic interposers, and silicon bridges. These decisions must be made much before the package layout stage, when there are many unknowns and risk is highest.

Apart from engineers, these concerns are shared by:

• system architects who evaluate key decisions
• engineering managers who are accountable for the schedule and risks
• technical executives responsible for platform decisions
• procurement teams evaluating EDA solutions

Other concerns include:

• Optimizing the package stack-ups
• Vertical power delivery for low voltage and high current applications
• pushing the SI constraints of high-speed D2D standards earlier up the design flow, and the risks of costly respins due to late discovery of SI issues
• lack of fast, accurate modeling, optimization, and validation solutions for productive design space exploration in the early phases, before the layout stage
• lack of advanced package modeling for chiplets and three-dimensional integrated circuits (3DICs)
• workflow and tool fragmentation between the architecture, layout, and SI teams
• reducing system design cycles by maintaining accuracy from schematic to tape-off

What are the limitations of traditional verification?

Figure 5. Traditional design workflow.

Traditional linear EDA workflows fail to address the above concerns of engineers and other stakeholders because of two deficiencies:

• High risk and computationally heavy post-layout driven workflow
• Lack of design optimization and verification before a full package layout

Traditional post-layout driven workflow makes the design optimization and verification process hard since it requires a very tedious workflow and computationally resource-heavy EM extractions. Especially, the challenges are amplified in the application of advanced package designs where silicon interposers and bridges are used with hatched grounds. They struggle to calculate the complex physics of hatched ground patterns.

However, most circuit-level pre-layout methods also lack the high-fidelity modeling accuracy required to predict high-speed D2D link margins and compliance with UCIe or BoW standards early in the design cycle.

Additionally, these traditional EDA tools do not seamlessly integrate interconnects with PHY-level compliance verification, forcing teams into manual, error-prone data integration.

Meanwhile, post-layout EM workflow lacks the required capabilities to bridge this gap. They are too slow and resource-heavy to be useful for rapid early-stage design exploration.

Keysight’s 3D interconnect design solution

Keysight addresses these limitations through next-generation design solutions for 3D interconnects in advanced packages. These solutions include:

1. Chiplet PHY Designer
2. Chiplet 3D Interconnect Designer
3. 3D Interconnect Designer

These solutions enable rapid design space exploration with fast, accurate insights based on physical designs without requiring a full package layout.