tag: PHY

The Evolution Of UCIe
By Ed Sperling - 02 Jun, 2026 - Comments: 0

Since it was released in March 2022, the Universal Chiplet Interconnect Express (UCIe) has grown from a basic way of connecting two dies together into a comprehensive specification that can ensure the handoff of data between various components in an advanced package, as well as validate the chiplets within that package. Mayank Bhatnagar, director of product marketing at Cadence, talks about the... » read more

How To Streamline Your Advanced Package Interconnect Designs
By Maria Castillo - 30 Apr, 2026 - Comments: 0

Monolithic system-on-chip (SoC) designs was once a popular choice. However, they face significant constraints in the era of AI. By forcing all chip functions into a single die and process node, they reduce engineering, manufacturing, and design cost flexibility. In contrast, the multi-die nature of chiplets enables different SoC functions to be designed and verified independently and fabrica... » read more

PCIe 8.0: Enabling The Next Generation Of High Bandwidth Systems
By Lou Ternullo - 09 Apr, 2026 - Comments: 0

As compute architectures evolve to support increasingly data‑intensive workloads, the role of high‑speed I/O has never been more critical. Artificial intelligence, high‑performance computing, hyperscale infrastructure, and advanced networking all depend on moving massive volumes of data efficiently, reliably, and at scale. The PCI‑SIG’s announcement of PCIe 8.0, which targets 256.0... » read more

Exploring The Latest Innovations In MIPI D-PHY And MIPI C-PHY
By Michael Nagib - 15 Jan, 2026 - Comments: 0

By Michael Nagib and Nuno Martins In the ever-evolving landscape of high-performance camera and display technologies, MIPI D-PHY and MIPI C-PHY specifications continue to lead the charge, setting benchmarks for low power, low latency, and high bandwidth data transmission. Building on the insights from our previous article, “Demystifying MIPI C-PHY/D–PHY Subsystem” – we now delve into... » read more

PCIe 8.0: Preparing For The Next Doubling
By Monica Olvera - 11 Dec, 2025 - Comments: 0

By Monica Olvera and Gustavo Pimentel Every few years, the industry confronts the same challenge: can general-purpose I/O double again without overwhelming power budgets, overwhelming signal-integrity limits, or fragmenting the ecosystem? With PCIe 8.0, the answer appears to be yes—if the entire stack continues to advance together. Public PCI-SIG information outlines an objective of 256.0 ... » read more

MIPI CSI-2 Provides The Backbone Of Automotive Sensor Networks
By Simon Bussières - 11 Dec, 2025 - Comments: 0

As the automotive sector accelerates toward higher levels of autonomy, the complexity and scale of sensor networks within vehicles are rapidly expanding. For semiconductor engineers, the challenge is not only to deliver high-performance silicon but also to ensure robust, scalable, and secure data transport across heterogeneous sensor arrays. The MIPI CSI-2 protocol has emerged as the de facto s... » read more

Achieving Reliable 2m+ DAC Connectivity For AI Scale Networks With 224G PHY IP
By Abhinav Kothiala - 16 Oct, 2025 - Comments: 0

As artificial intelligence workloads and hyperscale data centers continue to evolve, the requirements for networking infrastructure are becoming increasingly stringent. High-speed, reliable connectivity is essential to support the massive data flow and low-latency demands of AI-scale environments. Passive direct attach copper (DACs) remains an attractive choice for hyperscalers and system vendo... » read more

An Overview Of CXL Mode Alternate Protocol Negotiation
By Guo Yu - 28 Aug, 2025 - Comments: 0

The Peripheral Component Interconnect Express (PCIe) protocol has a very powerful feature called Alternate Protocol Negotiation (APN), which was introduced in the PCIe 5.0 specification. This feature allows the alternate protocols (non-PCIe) that use PCIe PHY layer to be enabled and provide their own implementation of the more abstract layers. One of the most common alternate protocols is th... » read more

Often Overlooked, PHYs Are Essential To High-Speed Data Movement
By Ann Mutschler - 17 Jul, 2025 - Comments: 0

Over the past couple of decades, the semiconductor industry has evolved from a supporting role for traditional verticals like mobile, automotive, and PCs to a foundational role in those markets, as well as in AI factories and hyperscale data centers. Underlying this transformation is the physical layer (PHY), which has emerged as a critical enabler for data transfer and communications. The P... » read more

Towards Base-Station-On-Chip: Wireless Communication Kernels On A RISC-V Vector Processor (TU Dresden, CeTI)
By Technical Paper Link - 10 Jun, 2025 - Comments: 0

A new technical paper titled "Towards a Base-Station-on-Chip: RISC-V Hardware Acceleration for wireless communication" was published by researchers at TU Dresden and Centre for Tactile Internet with Human-in-the-Loop (CeTI). Abstract "The evolution of 5G and the emergence of 6G wireless communication systems impose higher demands for computing capabilities and lower power consumption in the... » read more

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