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GUC GLink Test Chip Uses In-Chip Monitoring And Deep Data Analytics For High Bandwidth Die-To-Die Characterization


Advanced ASIC leader Global Unichip Corp (GUC) has developed GLink, a high-bandwidth, low-latency, and power-efficient die-to-die (D2D) interface. GLink offers the industry’s highest optimized interconnect solution for both CoWoS and InFO packaging technologies. The GUC and proteanTecs collaboration started with GUC’s second generation of GLink, known as GLink 2.0. The project target was... » read more

Co-Packaged Optics And The Evolution Of Switch/Optical Interconnects In Data Centers


Driven by a need to reduce power and increase bandwidth density in data center network switches and other devices, the data networking industry is moving toward adoption of co-packaged optics (CPO). This paper provides a brief overview of the history of copper and optical interconnects, the limitations of existing interconnect solutions, and the future of co-packaged optics, including the benef... » read more

Integrated Ethernet PCS And PHY IP For 400G/800G Hyperscale Data Centers


Ethernet has become the primary network protocol of choice for the required server-to-server communication in hyperscale data centers, as it allows hyperscalers to disaggregate network switches and install their software operating systems independently. Ethernet enables cost-effective, dense, open switches and networking technologies which reduce cost/power per bit with transistor scaling. Ethe... » read more

Will Automotive Ethernet Win?


As internal combustion engines are replaced by electric motors, and mechanical linkages increasingly replaced by electronic messaging, an in-vehicle network is needed to facilitate communication. Ethernet, amended for automotive and other time-sensitive applications, appears to be the network of choice. But is that choice a done deal? And will Ethernet replace all other in-car networks? The ... » read more

Best 112G SerDes IP Architecture


Real world operation of a serializer/deserializer (SerDes) in a hyperscale data center is very demanding and requires robust performance in challenging conditions such as multitude of channel insertion loss, extreme temperature cycles, different types of packages with different trace lengths and discontinuities, etc. Hence, meeting interference tolerance (ITOL) and jitter tolerance (JTOL) compl... » read more

Getting Ready For An Efficient Shift To PCI Express 6.0 Designs With Optimized IP


PCI Express (PCIe) 6.0 technology with key changes will bring about challenges that high-performance computing, artificial intelligence, and storage system-on-chip (SoC) designers will face. This article provides designers a summary of the major changes and how they can be handled to ensure a smooth and successful transition to PCIe 6.0. The three major changes in PCIe 6.0 that designers nee... » read more

112G SerDes Modeling And Integration Considerations


The ever-increasing demand for compute power and data processing in accelerators, intelligence processing units (IPUs), GPUs, as well as training and inference SoCs is driving the adoption of 112G SerDes PHY IP solutions. Ensuring a reliable Ethernet link and efficient integration are the most essential requirements that designers need to meet. IBIS-AMI modeling can help predict SerDes link per... » read more

Demystifying MIPI C-PHY / D-PHY Subsystem


The newest member of the MIPI PHY family, the C-PHY, arrived in October 2014 to a mixture of excitement and apprehension. How would this new C-PHY compare to the MIPI D-PHY and M-PHY? What would differentiate the C-PHY, and would it be compatible enough with the D-PHY so that both could coexist in a hybrid subsystem? Now, years later, the answers are clear. This article will lay out... » read more

Enabling Cost-Effective, High-Performance Die-to-Die Connectivity


System advances in accelerated computing platforms such as CPUs, GPUs and FPGAs, heterogeneous systems on chip (SoCs) for AI acceleration and high-speed networking/interconnects have all pushed chip integration to unprecedented levels. This requires more complex designs and higher levels of integration, larger die sizes and adopting the most advanced geometries as quickly as possible. Facing th... » read more

Power Impact At The Physical Layer Causes Downstream Effects


Data movement is rapidly emerging as one of the top design challenges, and it is being complicated by new chip architectures and physical effects caused by increasing density at advanced nodes and in multi-chip systems. Until the introduction of the latest revs of high-bandwidth memory, as well as GDDR6, memory was considered the next big bottleneck. But other compute bottlenecks have been e... » read more

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