Scaling to tens of millions of CPO units per year requires the industry to first settle on automated, cost-effective methods for electrical and optical testing.
Key Takeaways:
Integrating photonic and electrical ICs into co-packaged optics (CPO) requires multimodal test capabilities at package-level test (a.k.a. final test), a challenge made more difficult by the need to scale from one million to tens of millions of units per year.
With demand from data centers exploding, the promise of increased data rates and lower power consumption with CPO has become particularly attractive. But scaling up by at least an order of magnitude places stress on test manufacturing processes, from wafer to system-level test. CPO consists of both electrical and optical ICs, so a final test solution for the packaged part needs to test both cost-effectively. The problem is that today each CPO design is unique, and bespoke test-cell solutions are expensive.
Fig. 1: Components of co-packaged optics split between electronic chiplets, photonic chiplets, and a laser. Source: Amkor
Put in perspective, the chip industry is developing the testing instruments while the products themselves are still under development. “For package test of co-packaged optics, I don’t think anyone has all the answers yet — it’s a rapidly evolving space with constant changes in both the devices and the manufacturing flows,” said Ira Leventhal, vice president of research and venture at Advantest America. “As we move from engineering into high-volume manufacturing, the key challenge is managing that variability while still driving cost, throughput, and quality. Our focus is on developing flexible, scalable test architectures that can adapt to this evolution and provide a clear path to production readiness.”
The CPO product profile, just in terms of optical engine count and connector differences, adds complexity to test development and test cell design. On top of that, there are numerous options:
The number of optical engines — and there can be many — determines the number of laser sources. In addition, different test cell solutions are required to respond to handling needs, thermal management, device interface board design, and ATE instrumentation.
Final test of the packaged module comes after the wafer-level test for the optical and electrical ICs. While test content can shift left to ensure known-good die (KGD), final test is still needed because it provides immense value for assembly process yield learning.
Fig. 2: Test insertions for silicon photonics from wafer to system-level test. Source: Teradyne
Much can be accomplished by ATE. “Wafer-level testing offers unparalleled access to individual optical components via grating or edge couplers, allowing engineers to extract high-fidelity data, such as precise insertion loss (IL), polarization-dependent loss (PDL), and responsivity,” said Meg O’Brien, director of product engineering at Lightmatter. “This granular inspection acts as a low-cost defense, catching and discarding defective dies before they enter the expensive assembly phase. However, this stage suffers from limited operational coverage, as it cannot simulate how those components will behave together in a finalized system. Conversely, package-level and CPO module testing shift the focus toward full system coverage, evaluating end-to-end performance indicators like bit error rate (BER), eye diagrams, and link margins under realistic, heterogeneous thermal stresses. While this module-level insertion provides the ultimate validation of a functional product, it comes with a high cost of failed parts.”
2.5D packaging enables CPOs that integrate optical and electronic ICs (ASICs/XPUs) on an interposer and substrate. Consequently, the final test cell solution needs to integrate the optical and electrical tests such that both the individual components and the overall CPO system functionality are verified. This has implications for ATE instrumentation and device interface board (DIB) choices for both optical and electrical connections. For DIBs, the optical die presents a challenge because there are a plethora of optical connector designs.
“There’s a tradeoff between the flexibility of the test system and the need to drive optical power at the device,” shared Matt Griffin, senior product manager for the silicon photonics test group at Teradyne. “Customers may want to provide a large number of laser sources and switch between those laser sources to different channels or split between those laser sources. But that comes with a power tradeoff because every switch and splitter introduces insertion loss. So one of the challenges we are spending a lot of time solving is determining the right balance between flexibility of optical instrumentation while still meeting power requirements and optical signal integrity at the package level.”
Because CPO integration is so new, the industry has minimally invested in managing this additional test data. Yield issues can be more effectively addressed in manufacturing if all components have identifiers and test data is efficiently managed.
“Most of the conversation about CPO testing is still focused on the test cell itself — sockets, fiber alignment, handlers, fixtures. What is underappreciated is what happens to the data after the test runs,” said Aftkhar Aslam, CEO of yieldWerx. “Yield on a CPO unit is multiplicative because the part has to pass an electrical spec and an optical spec. But those two streams almost never end up in the same place. ATE drops STDF, optical engines drop CSV or XLS, OSAs (optical spectrum analyzers) have their own formats, and burn-in racks emit something else. Teams know their final yield number, but figuring out why it dropped takes weeks because they’re hunting across four or five silos just to assemble a single unit’s full picture. CPO is not going to scale from 10 million to 100 million units a year if that piece doesn’t get solved.”
Device interface boards
Device interface boards (DIBs) play a key role in a test cell. The difficulty with CPO testing primarily lies with signal loss. Product engineering teams grapple with several factors when designing a reliable interface to the DUT (device under test).
“Production device interface boards are prone to multiple issues,” said Vineet Pancholi, manufacturing test technologist at Amkor. “A carefully architected and designed DIB includes hooks for calibration and diagnostics. The round-trip optical path can suffer from losses that must be calibrated to achieve the desired accuracy at the DUT interface. DUT socketing challenges like warpage, co-planarity, coupling, and interference are attributes that must be well accounted for within the fixture design. Without a carefully designed fixture, there is a risk of misprocessing production volumes.”
Others also highlight the need to consider fiber alignment and warpage.
“Key physical challenges include managing the significant weight and warpage of large modules and protecting fragile fiber array units (FAUs) during handling,” said Lightmatter’s O’Brien. “Achieving high-volume production requires automating fiber alignment and managing polarization-dependent loss through six-degree-of-freedom active alignment. Optical connectivity during the test should address the variety of connection options, as well as the alignment challenges. Optical input alignment methods that are fast and repeatable are critical to enabling repeatable and reliable CPO tests. A high-volume manufacturing solution is not possible when a CPO module sees wide variation on the optical input signals.”
In addition, the diverse set of connectors in use, along with the number of optical engines per unique CPO, amounts to nearly a custom solution for each product.
“When you look at different CPO module designs they all have different numbers of optical connectors around the package,” said Teradyne’s Griffin. “Then, when you get into the details with CPO customers, the connector design itself differs between customers. There is no standardization of the connector design. In testing and interfacing optically with that device, you have to customize the motion and alignment system for that connector type that’s being used. This results in a high-fidelity optical connection so you can get good insertion loss during at-speed test of that device.”
Optical connector vendors typically align the optical fibers to the optical engine either horizontally or vertically. Alignment approaches can differ as well. High alignment accuracy helps ensure low signal loss. A wider tolerance window is desired for self-alignment. Approaches include:
“There’s just so much variation in the connector space, and at this point we don’t see a lot of narrowing it down to which ones are going to be the winners,” noted Leventhal. “As we move from solving the technical challenges to scaling up to the HVM challenges, the connector vendors that really thought ahead about design for manufacturability and design for testability in their designs will become the connectors of choice for the industry.” He added that, due to the product type, there will not be a single connector because the system dictates whether the horizontal or vertical connection is appropriate.
A primary design consideration for manufacturability/testability is making a viable optical connection. In the field, the number of contacts may be on the order of tens, while in manufacturing test, such a number is unacceptable. In a high-volume manufacturing setting, the higher the number of contacts before failure, the better. In addition, cleaning processes for optical connectors need to be implemented because a dust particle on a lens affects signal integrity.
A compromised connector can damage a device-under-test and decrease yield due to increased insertion loss. In addition, poor connector reliability increases downtime frequency to change out connectors on the DIB. This is where data analytics, with appropriate planning, can add significant value
“What I’d flag from the data side is that fixture variability — contact resistance, fiber coupling efficiency, polarization alignment — tends to show up in the yield data as if it were device variability,” said yieldWerx’s Aslam. “Practically, you end up needing DIB-aware features in your yield model — which board, which socket, which fiber port the unit was tested on. Without that decomposition, the engineering team spends a lot of time chasing things that aren’t actually happening in the CPO.”
CPO final test requires both electrical and optical connections on the tester to the DUT interface. In scaling from lab to factory-ready solutions, there are different instrumentation and interface setups. Test factories already have an existing test fleet for large SoCs. Thus, to meet the CPO test requirements, they need to decide whether to invest in new testers or add instrumentation to existing test cells. With the latter path, a module-based test handler solution can be pursued.
Fig. 3: HPC ATE setup, with split architecture comprised of tester and handler sides. Source: Advantest
“When customers are looking to scale, as an ATE company, we would love to sell our customers a whole brand-new set of test cells. But the reality is the test cells they have can be upgraded to test CPOs,” said Advantest’s Leventhal. “Our approach is the concept of an optical load board as a new layer. This optical load board sits between the tester, the test socket, and the electrical load board side and the handler side. The handler not only performs the ‘pick and place,’ it also supplies the thermal management. In between those two layers, we put an optical load board as a layer. It holds the optical signaling, external lasers, and manages the mechanical connection to the connectors. The whole purpose of this approach is compatibility with the existing installed base. We don’t need to ask our customers to retool hundreds or even thousands of testers to test CPOs.”
Fig. 4: HPC with CPO ATE setup, architecture refactored into layers, each handling specific and distinct functions. Source: Advantest
Integrating optical and electrical instrumentation
Testing CPO requires testing for optical and electrical attributes, both separately and in concert. The test content list for CPO covers a wide range of both electrical and optical stimuli and measurements. Integration of electrical and optical instrumentation is not yet fully realized, presenting opportunities for further development.
Fig. 5: Package-level test. Source: Amkor
“ATEs are seriously lacking a seamless integration of optical instrumentation – tunable lasers, photon power meters, switches, muxes, SMUs, and VNAs,” observed Amkor’s Pancholi. “Most of the ATEs are also lacking the right count of optical I/O to support efficient single-site production testing. There appears to be adequate wavelength support with adequate dynamic range (O-band: 1,260 to 1,360nm; C-Band: 1,530 to 1,565nm). The supply base is working on resolving all these aspects. We are expecting all of this to be resolved over time. No known showstoppers are expected along the way.”
There still are integration problems to solve for hardware, software, and data management. Starting with hardware, how many optical instruments are required?
An ATE needs to support the number of channels per optical instrument with lasers for stimulus and measurement. “We need to add optical instrumentation. But when you go to the next layer, there’s a lot of complexity underneath,” said Teradyne’s Griffin. “How do I flexibly spread channel count to my device, and how do I optically connect to that device? It’s certainly a new challenge, but it’s one we are already solving.”
Furthermore, the number and types of lasers increase in proportion to the number of optical engines. “To optically power up just one optical engine, you need between 4 and 8 lasers. In the final module you may have 16 to 32 optical engines. That’s 64 to 128 lasers, so providing that number of laser sources to test that package is an important challenge to solve, as well,” noted Griffin. “I’ll add one more challenge — the shift to CWDM or DWDM (coarse or dense wavelength division multiplexing), where they have multiple wavelengths per fiber. This drives the laser source count even higher.”
More optical engines on a CPO coupled with a large XPU means more data. Integration of data facilitates yield learning. However, it can be cumbersome.
“The one thing worth saying from the data side is that dual-domain ATEs — testers that emit a single tester record with both electrical and optical results in it — make the downstream analytics dramatically simpler,” said yieldWerx’s Aslam. When you’ve got separate electrical and optical testers running sequentially, the analytics team has to re-stitch records on serial number and timestamp, and there’s risk every time you do that. So one of the easier ATE improvements isn’t necessarily more measurement capability. It’s more discipline in how the data comes out.”
ATE vendors are working toward that goal. “Today, we integrate optical instrumentation into our software to support photonics testing. We will be able to correlate and synchronize data between electrical and optical instrumentation. We are working on new visualization tools and analysis tools to support both optical and electrical test data,” said Griffin.
Conclusion
Scaling from one million to tens of millions of shipped units per year will not occur without reliable device interface boards, good data management practices, and automated ATEs with seamless integration of optical and electrical instrumentation. Additional development is needed for a manufacturable solution that is effective at a reasonable cost, but no showstoppers have been noted by industry experts.
“If you’d asked me a year or two ago, I would have said, ‘It’s still the Wild West.’ But we’re seeing customers that plan to drive significant volume,” said Teradyne’s Griffin. “And yes, there are challenges that need to be figured out. But there’s a significant momentum to make this work, because of the power savings in the data center. We see how much growth and innovation are happening in this market, especially for test and measurement.”
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