Too Much Fab And Test Data, Low Utilization


Can there be such a thing as too much data in the semiconductor and electronics manufacturing process? The answer is, it depends. An estimated 80% or more of the data collected across the semiconductor supply chain is never looked at, from design to manufacturing and out into the field. While this may be surprising, there are some good reasons: Engineers only look at data necessary to s... » read more

Infrastructure Impacts Data Analytics


Semiconductor data analytics relies upon timely, error-free data from the manufacturing processes, but the IT infrastructure investment and engineering effort needed to deliver that data is, expensive, enormous, and still growing. The volume of data has ballooned at all points of data generation as equipment makers add more sensors into their tools, and as monitors are embedded into the chip... » read more

Why Data Format Slows Chip Manufacturing Progress


The Standard Test Data Format (STDF), a workhorse data format used to pull test results data from automated test equipment, is running out of steam after 35 years. It is unable to keep up with the explosive increase in data generated by more sensors in various semiconductor manufacturing processes. First developed in 1985 by Teradyne, STDF is a binary format that is translated into ASCII or ... » read more

Blog Review: Feb. 12


Complexity is growing by process node, by end application, and in each design. The latest crop of blogs points to just how many dependencies and uncertainties exist today, and what the entire supply chain is doing about them. Mentor's Shivani Joshi digs into various types of constraints in PCBs. Cadence's Neelabh Singh examines the complexities of verifying a lane adapter state machine in... » read more

Network Storage Optimization In Chip Design


Prathna Sekar, technical account manager at ClioSoft, explains how to manage large quantities of data, how this can quickly spin out of control as colleagues check in data during the design process, and how to reduce the amount that needs to be stored. » read more

Reducing Data At The Source


Jens Döge, group manager for image acquisition and processing in Fraunhofer IIS’ Engineering of Adaptive Systems Division, talks about how to slash the amount of data that needs to be sent to the cloud or edge for processing by focusing only on the regions of interest in an image, and how that reduces the cost of moving that data. » read more

Utilizing More Data To Improve Chip Design


Just about every step of the IC tool flow generates some amount of data. But certain steps generate a mind-boggling amount of data, not all of which is of equal value. The challenge is figuring out what's important for which parts of the design flow. That determines what to extract and loop back to engineers, and when that needs to be done in order to improve the reliability of increasingly com... » read more

Collaborative IC Design Mandates Integrated Data Management


Over the last decade, design teams have encountered increased competition due to globalization (requiring the best available engineers irrespective of location), an exponential increase in design complexity, and shrinking market windows. This results in teams of engineers with different skill sets (for example analog, digital, MEMS, and RF), spread across multiple sites, managing complex flows,... » read more

Week in Review: IoT, Security, Auto


Internet of Things Internet of Things vendors and providers of network services need to collaborate to fully realize the possibilities presented by the IoT, Chris Martin of PowWowNow writes. “The potential applications for IoT sensors and devices span a vast number of industries, with IoT technologies expediting the growth of smart cities, autonomous vehicles and connected industry technolog... » read more

Collaborative IC Design Mandates Integrated Data Management


Due to complexity and multi-domain expertise, custom IC design typically requires a team to successfully design and verify the project. Often, specific blocks are assigned to team members based on analog, digital, MEMS, RF expertise, across multiple geographies, and separate verification team members focus on block and system validation. This means that unstructured design files with multiple c... » read more

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