Transforming Test For Co-packaged Optics

Data centers are undergoing a dramatic transformation to reduce the power consumption of high-speed data transmissions by 70% or more with co-packaged optics. By moving optical transceivers from the fronts of racks into the same package as the networking switch and HBMs, AI programs that used to take a week to run can now be completed in a day.

To enable this change in production manufacturing, testing platforms must deliver automated, scalable processes that achieve comparable test coverage for photonic devices to that of electronic ICs. Despite the investment needed to make this happen, the rewards behind breaking this interconnect bottleneck in data centers, 5G, and IoT applications appear to be worth the effort.

Most significantly, leading providers of AI and HPC devices like NVIDIA and Intel are pursuing a variety of probing methods, fiber alignment strategies, and connector approaches to determine the best methods for testing at the wafer, package, and system levels.

“Silicon photonic-based optical I/O chiplets are typically designed with dense wavelength division multiplexing (DWDM), allowing higher data bandwidth scaling per fiber port than their optical engine counterparts in pluggable transceivers,” said Mark Gardner, vice president and general manager of the Advanced System Assembly & Test Business Group at Intel. “Additionally, these chiplets are becoming smaller in size due to advances in silicon photonic device miniaturization, allowing their co-integration with the compute node in an advanced package with electrical signaling distance as low as 100µm.”

This is driving the buzz around photonics. “Interest in silicon photonics and CPO testing has been picking up sharply over the last two to three years, which goes hand-in-hand with the shift of the industry to focus on data center and enabling applications like Chat GPT and generative AI,” said Clemens Leichtle, director, optical business lead at Advantest. “That’s the killer application that really brings CPO to the forefront of technology development today.”

This focus touches all sectors of the industry, from design to reliability testing and in-field surveillance. “We’re seeing a tremendous amount of interest in test and measurement of silicon photonics and co-packaged optics from chip designers, OSATs, foundries, and silicon photonic startups,” said Matt Griffin, senior product manager of optoelectronics test at Teradyne. “Testing these devices requires adding optical test coverage at almost every test insertion using a variety of optical instruments.”

Bottom-line cost for data centers will be significantly lower using co-packaged optics. “CPO technology offers three critical advantages over traditional pluggable optical transceivers — significant power efficiency, unprecedented bandwidth density, and compelling economics — all contributing to a compelling ROI for AI-centric data center operators,” said David Clark, vice president of product marketing at Amkor Technology.

Companies are collaborating across the supply chain because no single organization has all the expertise needed for CPO testing. Teradyne announced its acquisition of Quantifi Photonics earlier this year, while Advantest is partnering with FormFactor on CPO testing.

Importantly, a lack of automation in photonics testing is undergoing a significant revamping from reliance on a collection of benchtop instruments from multiple vendors to producing automated, scalable testers for photonic integrated circuits (PICs), waveguides, and other optical components. “Today, we see laser sources, optical power meters, and polarization control being used to perform optical DC testing,” said Griffin.

In data centers, copper has become the weak link that connects plug-in optical transceivers at the rack front to the GPU/HBM-based AI chips (see figure 1, top illustration). The main reason behind pluggable optical transceivers is the poor reliability of III-V lasers, enabling a swap when the laser fails. “Photodiode receivers and passive optics are typically far more reliable than the laser source transmitters and thus are integrated within the PIC die,” said Clark. “Lasers run hotter, wavelengths drift with aging, epitaxial defects propagate with time and heat, etc. For these reasons, the hyperscale system designers are choosing to go with remote laser source architectures.”

Optical engines contain photodetectors, waveguides, and PICs containing modulators. The leading modulator type is micro-ring-based. It converts electrical signals to optical signals while also controlling the delivery of those optical signals. In cases where the optical engine is integrated on the interposer, waveguides and other optical components may be built into the substrate.

Fig. 1: Photonics harnesses the speed of light for faster data transmission. Source ASE

While the timeline for high-volume production of co-packaged optics is unknown, what’s clear is that there are three top challenges for test. “First, optical probing requires a very tight alignment of the fibers that transfer the data from the device to the measurement instruments, and vice versa,” said Leichtle. “To do this, alignment of the optical probes with the optical I/Os on the device is being approached in different ways using passive or active alignment.”

This needs to be done automatically, and with great consistency. “When it comes to testing in a production environment, you have to connect a fiber and push it into that connector, and that should be done in an automated way,” Leichtle said. “Some customers are pursuing vertical launch, pushing the connector from the top down, or horizontal launch, pushing the fiber from the side into the connector. Today, this is mostly a manual task.”

There’s more than one way to approach this, too. “An alternative approach being pursued across the industry is to introduce a detachability point at the package edge, where an optical connector can be interfaced to the photonic IC,” said Intel’s Gardner. “This can be achieved using an intermediate glass bridge that is directly attached to the PIC, allowing use of a detachable optical connector. This allows the optical interface to be directly tested prior to assembly, only committing the package in a known-good state.”

Regardless of the approach, the system requires optical instruments to deliver, condition and measure the optical signals using lasers that generate the light, switches and couplers that guide the light, polarization controllers and attenuators to modify the light, reference modulators that convert optical signals to electronic signals or vice versa, as well as optical power meters to track the strength of the light.

Test insertions
Regardless of test step, interfacing with the device is the key step. “The other major innovation involves determining the best way to optically interface to the device under test: optical alignment at wafer probe with sub-micrometer precision or connector automation for optical engine and CPO testing,” said Griffin.

Within testing, thermal management is as major an issue as it is for CPO system operation. “One of the interesting things about the photonic IC is that it is very sensitive to thermal. So as it heats up, you can have some optical losses, which means you get data loss,” said Mark Gerber, senior director at ASE. “The photonic IC itself doesn’t really generate any heat, but the laser source generates 10 to 12 watts. And you may have 8 or 16 lasers, so it adds up. Then you have the heat generated by the controller die in the optical engine, as well as the GPU or ASIC. So you’ve got multiple thermal sources coming into play, and it’s a significant challenge to keep things cool.”

Testing starts with a wafer-level insertion of the photonic IC itself, which contains hundreds of optical components. “Here we mostly see both electrical and optical DC measurements. People are interested, for example, in characteristics like the losses with respect to the applied wavelength, so wavelength dependent losses, or polarization-dependent losses. And it is very important to characterize a photodiode with a so-called dark current measurement where you turn off the laser input and measure the resulting leakage current. After that, usually the photonic IC is integrated with some electronic IC, where you can do additional electro-optical measurements. Eventually, this is singulated, and people talk about an optical engine. And before the optical engine is co-packaged with some very expensive SoC device, people want to do a very thorough testing to ensure you have a known-good optical engine. This is typically the test stage where people look for at-speed test conditions, a very high speed test where the modulators are stressed to the maximum,” said Leichtle.

Higher throughput may be achieved by attaching the fiber(s) at a later stage. “Optical couplers that can be aligned to the PIC die allow mechanical fiber attach to occur later in the system assembly process,” Clark said. “In some cases, this may still require active alignment with an integrated light feedback loop being used. However, the fiber pigtail will not be present, which is more amenable to HVM. Dedicated equipment is still required, but the overall assembly process is far more streamlined than the old methods of direct fiber attach.”

One tool that helps improve the alignment process is simulation. “We are starting to use simulation software to model coupling between the optical probes and the device under test,” said Griffin. “Early on, we would typically get the customer’s design specs, design an optical probe for those specifications, and then we would find out the performance when we physically implemented the test procedure. But now we’re trying to model the optical probe as well as the customer’s device characteristics to predict the probe performance and optimize the design before we implement it.”

Eventually, optical probing can take place on the same equipment using electro-optical probe cards. “This means that the probe cards also integrate the optical probes mechanically, with possibly active alignment capabilities as well. I expect this approach will gain traction going forward because then there’s no need to buy dedicated optical probers, and you can use the installed base of electrical probers,” Leichtle said. “Because you start with the electrical alignment and the needles of the probe card are aligned to the electrical pads, optical alignment can benefit from this electrical alignment.”

Testing must address both 2.5D and 3D implementations. “In some cases, we are seeing photonics ICs and electronics ICs on the same wafer. In that case, there are electrical paths and optical couplers on the top side of the wafer, enabling probes both optically and electrically from one side of the wafer,” said Griffin. “Then there are other publicly available manufacturing processes that advertise the ability to build a photonics IC on one wafer, the electronics IC on another wafer, and bond these together. At this point, there are electrical pads on one side of the wafer and optical couplers on the other side, which then requires two-sided probing.”

Another change involves determining the best place to perform at-speed testing. “Where the at-speed testing takes place, which normally occurs at package test, is still open to debate,” Griffin said. “We’re seeing this testing move to the wafer level, what we call shift left, but there are definitely challenges with the probe technology and also optical-electrical conversion to ensure at-speed testing. For instance, an optical transceiver in die form on the wafer gets singulated and then co-packaged with a high-performance compute device. The price points of those two devices are materially different. The GPU or AI ASIC is substantially more expensive than the optical engines, so ensuring only known good optical transceivers before co-packaging is essential.”

Controlling temperatures
It’s well understood that good chips/chiplets depend on good neighbors in the same or different packages. “Optical transceivers for co-packaged applications will be packaged next to extremely high-temperature, high-performance computing devices. Over the next several years, these GPUs and AI ASICs will consume thousands of watts, so understanding the response of these devices in high temperature settings where they’ll be operating is critical,” Griffin said. “Eventually, we’ll see a few companies with very high-volume manufacturing capabilities set standards, particularly for connector design, resulting in higher volume optimized handling and connector alignment solutions. In the meantime, ATE suppliers must deliver flexible, customizable optical interfaces, while delivering the optical instruments needed for critical measurements in high-volume testing environments.”

Photonic devices must deal with changes in thermal expansion of materials, which can change the resonance frequency of modulators, among other things. “Important characteristics like the reflective index of a material show some rather strong temperature dependency, and this is particularly pronounced for micro-ring modulators,” said Leichtle.

DFT
Design for test methodologies will help define how, when, and where to test to make sure these devices work as expected. DFT can reduce costs and improve coupling, but as its name implies, it needs to be developed early in the design process so it can be implemented wherever and whenever it makes sense.

“There are two main capabilities for DFT,” said Griffin. “These optical loop-backs can then be used to perform certain calibrations of optical inputs to the device. Devices in the end application may be edge coupled, but we’re also seeing vertical coupling structures integrated because vertical probing is easier at the wafer.”

These devices are converting electrical to optical, or optical to electrical signals, at extremely high data rates. “Typically, transceivers are tested using a variety of bit error rate test techniques, eye diagram measurements, and potentially some type of RF measurements,” Griffin said. “However, this instrumentation is historically expensive, so more and more we’re seeing implementations that can generate and receive data at-speed from the device itself. Testing still requires an optical interface with the device, though, with optical loop-back so the device can self-test at speed.”

Optical engines testing ensures that only known-good optical transceivers are co-packaged. “In the end, we are talking about testing of electro-optical transceivers, so you have to provide on the electrical side the data for the modulators, and especially at some later test insertion you want to test those modulators at-speed,” said Leichtle. “Some applications today talk about 200 gigabits/second data rates, which is extremely fast, and the required electrical instruments to provide that are expensive, especially if you need to probe those electrical signals. Signal integrity is a big problem. We recommend that our customers implement a BiST engine, which provides the electrical inputs to the modulators, so that you don’t have to use external instruments. This is really a BiST engine on the electrical side, providing the data to the modulators on the driver side, then looping back on the optical side and comparing the transmission and receiving sides. This kind of BiST is very, very favorable for testing.”

Standards, eventually
As with all new approaches, ensuring reliability takes time to understand what can go wrong and to ultimately develop standards to guarantee predictable results. But standards also require a balancing act between the need for predictability and the need to experiment with a nascent technology.

Today, multiple companies are configuring packages in different ways, with edge couplers or surface couplers, and with proprietary connectors. The connector structure is being worked on by system designers, optical connector makers, and start-up firms. So when it comes to optimizing the optical interface to the DUT, there will be custom automation solutions for the time being.

Ultimately, that will change because without a standard plug-in, automating multiple tasks is especially difficult. And because these devices are expected to function predictably throughout their lifetimes, silicon lifecycle management (SLM), which is being increasingly adopted for electronic ICs, also will be applied to photonic devices. Using monitors embedded within devices, the industry can gain insights regarding how they perform in the field and may be improved.

“The same principles must be applied, perhaps even more rigorously than electronic circuits, to photonic ICs and photonic interposers, but with a new set of monitoring structures for a new set of metrics,” said Teng-Kiat Lee, technical product management director at Synopsys. “For example, the ability to make optical power measurements without impacting device operations is critical.”

Lee noted that thermal sensors can be coupled with other performance sensors to feed back how real-life operating conditions affect device operation and performance.

Conclusion
Combining electronic IC and photonic IC testing is a significant challenge, and there are multiple options today for performing alignment and connector design, as well as different testing approaches. But the ongoing build-out of hyperscaler data centers charged with minimizing energy use creates a formidable driver for these technology developments.

Standards will help implement higher levels of automation for photonics and CPO testing, but most sources expect standards to take at least two or three years to develop. The largest foundries and players are expected to adopt rules that will ensure proper yield and functionality, but customizable optical interfaces based on a customer’s design will prevail in the short term. Once the connector and other aspects are standardized, there will be more leverage in terms of providing higher volume optimized handling and connector alignment solutions.

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